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Wed, 13 Dec 2023 21:30:36 +0000 (GMT) Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA05.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 3BDLUZxj002505 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 13 Dec 2023 21:30:35 GMT Received: from jesszhan-linux.qualcomm.com (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Wed, 13 Dec 2023 13:30:34 -0800 From: Jessica Zhang Subject: [PATCH v4 0/2] drm/msm/dpu: INTF CRC configuration cleanups and fix Date: Wed, 13 Dec 2023 13:30:16 -0800 Message-ID: <20231213-encoder-fixup-v4-0-6da6cd1bf118@quicinc.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit X-B4-Tracking: v=1; b=H4sIAGgiemUC/33MQQ6CMBCF4auQrq3pTClBV97DuIDpIF0I2kqjI dzdQkyMxLh8M/n+UQT2joPYZ6PwHF1wfZdGvskEtVV3Zuls2gIVagBEyR31lr1s3GO4ygIIdqq GQpVGJHP1nB5L73hKu3Xh3vvnko8wX98lrValCFJJUxoyOVmVF3y4DY5cR1vqL2JuRfx4BL32m HwNUOWV1YbND6//ej17QxbJVkXdmG8/TdML+mBl+iwBAAA= To: Rob Clark , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , "Daniel Vetter" CC: , , , , , Jessica Zhang X-Mailer: b4 0.13-dev-53db1 X-Developer-Signature: v=1; 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Wed, 13 Dec 2023 13:30:58 -0800 (PST) This series drops the frame_count and enable parameters (as they're always set to the same value). It also sets input_sel=0x1 for INTF. --- Changes in v4: - Moved comment about input_sel to outside of dpu_hw_setup_misr() - Link to v3: https://lore.kernel.org/r/20231213-encoder-fixup-v3-0-b5cd2cda6bf5@quicinc.com Changes in v3: - Changed input_sel to u8 - Link to v2: https://lore.kernel.org/r/20231213-encoder-fixup-v2-0-b11a4ad35e5e@quicinc.com Changes in v2: - Switched patch order - Changed input_sel parameter from bool to u8 - Link to v1: https://lore.kernel.org/r/20231130-encoder-fixup-v1-0-585c54cd046e@quicinc.com --- Jessica Zhang (2): drm/msm/dpu: Set input_sel bit for INTF drm/msm/dpu: Drop enable and frame_count parameters from dpu_hw_setup_misr() drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 4 ++-- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 4 ++-- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c | 6 +++--- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h | 4 ++-- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c | 6 +++--- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.h | 3 ++- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c | 20 ++++++++------------ drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h | 8 +++----- 8 files changed, 25 insertions(+), 30 deletions(-) --- base-commit: 0d9372c346d4cdf347354382e0659de8c1cc0236 change-id: 20231122-encoder-fixup-61c190b16085 Best regards, -- Jessica Zhang