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Wed, 13 Dec 2023 14:47:51 -0800 (PST) From: Charlie Jenkins Subject: [PATCH v3 0/2] riscv: Create and document PR_RISCV_SET_ICACHE_FLUSH_CTX prctl Date: Wed, 13 Dec 2023 14:47:46 -0800 Message-Id: <20231213-fencei-v3-0-b75158238eb7@rivosinc.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 8bit X-B4-Tracking: v=1; b=H4sIAJI0emUC/12MQQ7CIBBFr9KwFsMMpq2uvIdxUehgZyEYMETTc Hdpo8a4fD//vVkkikxJHJpZRMqcOPgKetMIOw3+QpLHygIVagDopCNviaXbu1aNXb9zgxL1fIv k+LGGTufKE6d7iM+1m2FZ3wnETyKDVNKQVT2ANQh4jJxDYm+3NlzFUsn4Y2r1NbGaaE2LejBgw P2ZpZQXYFRh/9kAAAA= To: Paul Walmsley , Palmer Dabbelt , Albert Ou , Jonathan Corbet , Conor Dooley , =?utf-8?q?Cl=C3=A9ment_L=C3=A9ger?= Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, Charlie Jenkins X-Mailer: b4 0.12.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1702507670; l=1448; i=charlie@rivosinc.com; s=20231120; h=from:subject:message-id; bh=/YlQ8qL8rFNrU4HyEupJRRntb59YBilc0ngS06eVjfE=; b=jwleU1mQbFQCVc8gBuGN2sz2YjwjLX2t4LgnF5VYuL/LUu7TfGfh9AgGss4pWe4XF+aafVadm 1D/TRXdPTnKCmqHPKcxuSadEhpKsYxnHp3FyETHGk34qPGGwR6XIfO6 X-Developer-Key: i=charlie@rivosinc.com; a=ed25519; pk=t4RSWpMV1q5lf/NWIeR9z58bcje60/dbtxxmoSfBEcs= X-Spam-Status: No, score=-0.8 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_HELO_NONE, SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on agentk.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (agentk.vger.email [0.0.0.0]); Wed, 13 Dec 2023 14:48:07 -0800 (PST) Improve the performance of icache flushing by creating a new prctl flag PR_RISCV_SET_ICACHE_FLUSH_CTX. The interface is left generic to allow for future expansions such as with the proposed J extension [1]. Documentation is also provided to explain the use case. [1] https://github.com/riscv/riscv-j-extension Signed-off-by: Charlie Jenkins --- Changes in v3: - Check if value force_icache_flush set on thread, rather than in mm twice (Clément) - Link to v2: https://lore.kernel.org/r/20231130-fencei-v2-0-2cb623ab1b1f@rivosinc.com Changes in v2: - Fix kernel-doc comment (Conor) - Link to v1: https://lore.kernel.org/r/20231122-fencei-v1-0-bec0811cb212@rivosinc.com --- Charlie Jenkins (2): riscv: Include riscv_set_icache_flush_ctx prctl documentation: Document PR_RISCV_SET_ICACHE_FLUSH_CTX prctl Documentation/arch/riscv/cmodx.rst | 98 ++++++++++++++++++++++++++++++++++++++ Documentation/arch/riscv/index.rst | 1 + arch/riscv/include/asm/mmu.h | 2 + arch/riscv/include/asm/processor.h | 6 +++ arch/riscv/mm/cacheflush.c | 37 ++++++++++++++ arch/riscv/mm/context.c | 8 ++-- include/uapi/linux/prctl.h | 3 ++ kernel/sys.c | 6 +++ 8 files changed, 158 insertions(+), 3 deletions(-) --- base-commit: b85ea95d086471afb4ad062012a4d73cd328fa86 change-id: 20231117-fencei-f9f60d784fa0 -- - Charlie