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Date:   Thu, 14 Dec 2023 17:33:54 +0200
From:   Abel Vesa <abel.vesa@linaro.org>
To:     Konrad Dybcio <konrad.dybcio@linaro.org>
Cc:     Andy Gross <agross@kernel.org>,
        Bjorn Andersson <andersson@kernel.org>,
        Rob Herring <robh+dt@kernel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
        Conor Dooley <conor+dt@kernel.org>,
        linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org,
        linux-kernel@vger.kernel.org,
        Rajendra Nayak <quic_rjendra@quicinc.com>
Subject: Re: [PATCH 1/2] arm64: dts: qcom: x1e80100: Add all missing nodes
Message-ID: <ZXsgYl2h+MnTIz7D@linaro.org>
References: <20231212-x1e80100-dts-missing-nodes-v1-0-1472efec2b08@linaro.org>
 <20231212-x1e80100-dts-missing-nodes-v1-1-1472efec2b08@linaro.org>
 <9c8e887b-429c-4226-9851-5f1cbb93524a@linaro.org>
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On 23-12-12 17:21:19, Konrad Dybcio wrote:
> 
> 
> On 12/12/23 11:24, Abel Vesa wrote:
> > Add all missing nodes which describe entire X1E80100 platform.
> "all" doesn't really mean all :|
> 

Well, all the nodes where we have support working (for now).

But I'll re-word it to say "add some missing nodes".

> couple of patch-wide observations below
> 
> [...]
> 
> > +		gpucc: clock-controller@3d90000 {
> > +			compatible = "qcom,x1e80100-gpucc";
> > +			reg = <0 0x3d90000 0 0xa000>;
> Please make sure the address part is padded to 8 hex digits

Will do.

> [...]
> 
> > +		usb_1_ss2_hsphy: phy@fde000 {
> > +			compatible = "qcom,x1e80100-snps-eusb2-phy",
> > +				     "qcom,sm8550-snps-eusb2-phy";
> > +			reg = <0x0 0x0fde000 0x0 0x154>;
> and please choose 0x0 vs 0 and stick to one (which seems to
> be 0 in this file)

I'll use 0x0 in all reg as I think this is more consistent.

> 
> [...]
> 
> > +		pcie6a: pci@1bf8000 {
> > +			device_type = "pci";
> > +			compatible = "qcom,pcie-x1e80100";
> > +			reg = <0x0 0x01bf8000 0x0 0x3000>,
> > +			      <0x0 0x70000000 0x0 0xf1d>,
> > +			      <0x0 0x70000f20 0x0 0xa8>,
> > +			      <0x0 0x70001000 0x0 0x1000>,
> > +			      <0x0 0x70100000 0x0 0x100000>;
> > +			reg-names = "parf", "dbi", "elbi", "atu", "config";
> one per line, please

Will do.

> 
> > +			#address-cells = <3>;
> > +			#size-cells = <2>;
> > +			ranges = <0x01000000 0x0 0x00000000 0x0 0x70200000 0x0 0x100000>,
> > +				 <0x02000000 0x0 0x70300000 0x0 0x70300000 0x0 0x3d00000>;
> > +			bus-range = <0x00 0xff>;
> > +
> > +			dma-coherent;
> > +
> > +			linux,pci-domain = <7>;
> > +			num-lanes = <2>;
> > +
> > +			interrupts = <GIC_SPI 773 IRQ_TYPE_LEVEL_HIGH>;
> > +			interrupt-names = "msi";
> > +
> > +			#interrupt-cells = <1>;
> > +			interrupt-map-mask = <0 0 0 0x7>;
> > +			interrupt-map = <0 0 0 1 &intc 0 0 0 843 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
> > +					<0 0 0 2 &intc 0 0 0 844 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
> > +					<0 0 0 3 &intc 0 0 0 845 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
> > +					<0 0 0 4 &intc 0 0 0 772 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
> you can drop these comments

Will do.

> [...]
> 
> > +				clocks = <&gcc GCC_DISP_AHB_CLK>,
> > +					 <&gcc GCC_DISP_HF_AXI_CLK>,
> > +					 <&dispcc DISP_CC_MDSS_AHB_CLK>,
> > +					 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
> > +					 <&dispcc DISP_CC_MDSS_MDP_CLK>,
> > +					 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
> > +				clock-names = "bus",
> > +					      "nrt_bus",
> > +					      "iface",
> > +					      "lut",
> > +					      "core",
> > +					      "vsync";
> you probably should list the ROT clock here too

Will look into it.

> [...]
> 
> > +		cpucp_mbox: mailbox@18830000 {
> > +			compatible = "qcom,x1e80100-cpucp-mbox", "qcom,cpucp-mbox";
> This is not upstream

It's a new driver, so bindings patches will come with it.

> 
> > +			reg = <0 0x18830000 0 0x300>, <0 0x17430000 0 0x4C08>;
> lowercase hex

Will do.

> 
> Konrad