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Thu, 14 Dec 2023 23:38:54 +0000 Received: from SJ1PR11MB6083.namprd11.prod.outlook.com ([fe80::2b58:930f:feba:8848]) by SJ1PR11MB6083.namprd11.prod.outlook.com ([fe80::2b58:930f:feba:8848%6]) with mapi id 15.20.7068.038; Thu, 14 Dec 2023 23:38:54 +0000 From: "Luck, Tony" To: Daniel Ferguson , "rafael@kernel.org" , "lenb@kernel.org" , "james.morse@arm.com" , "bp@alien8.de" , "pabeni@redhat.com" , "linmiaohe@huawei.com" , "rostedt@goodmis.org" , "leoyang.li@nxp.com" , "luoshengwei@huawei.com" CC: "linux-acpi@vger.kernel.org" , "linux-edac@vger.kernel.org" , "linux-kernel@vger.kernel.org" Subject: RE: [PATCH RESEND v3 1/1] RAS: Report ARM processor information to userspace Thread-Topic: [PATCH RESEND v3 1/1] RAS: Report ARM processor information to userspace Thread-Index: AQHaLuSgz1v/s4k9/k+lw9lC4B057LCpbbIAgAABRyA= Date: Thu, 14 Dec 2023 23:38:54 +0000 Message-ID: References: <20231214232330.306526-1-danielf@os.amperecomputing.com> <20231214232330.306526-2-danielf@os.amperecomputing.com> In-Reply-To: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=intel.com; 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charset="us-ascii" Content-Transfer-Encoding: quoted-printable Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: SJ1PR11MB6083.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: de218ac3-4504-4011-42cf-08dbfcfdd59c X-MS-Exchange-CrossTenant-originalarrivaltime: 14 Dec 2023 23:38:54.3146 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: pjdqRHBHRARwZfzZB3GdB5TbNt41Y4C1yAA7+bfra4vaWCx73DR32o/OF8pe8SU1o/tcj8aGzP/YrZajrynpyA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA2PR11MB5036 X-OriginatorOrg: intel.com > What GIT tree is this patch based on? I don't see this log_arm_hw_error() > function in drivers/ras/ras.c upstream, or in intel-next. Thirty seconds after hitting SEND, I see I was looking at the wrong GIT tre= e. This code is based on upstream. Ooops. > Should ARM specific code like this be in a file with "arm" in its name? O= r at least > be inside some #ifdef CONFIG_ARM. But I stand by this part. -Tony