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Thu, 14 Dec 2023 18:28:20 -0800 Date: Thu, 14 Dec 2023 18:28:18 -0800 From: Nicolin Chen To: "Tian, Kevin" CC: "Liu, Yi L" , "joro@8bytes.org" , "alex.williamson@redhat.com" , "jgg@nvidia.com" , "robin.murphy@arm.com" , "baolu.lu@linux.intel.com" , "cohuck@redhat.com" , "eric.auger@redhat.com" , "kvm@vger.kernel.org" , "mjrosato@linux.ibm.com" , "chao.p.peng@linux.intel.com" , "yi.y.sun@linux.intel.com" , "peterx@redhat.com" , "jasowang@redhat.com" , "shameerali.kolothum.thodi@huawei.com" , "lulu@redhat.com" , "suravee.suthikulpanit@amd.com" , "iommu@lists.linux.dev" , "linux-kernel@vger.kernel.org" , "linux-kselftest@vger.kernel.org" , "Duan, Zhenzhong" , "joao.m.martins@oracle.com" , "Zeng, Xin" , "Zhao, Yan Y" Subject: Re: [PATCH v7 1/3] iommufd: Add data structure for Intel VT-d stage-1 cache invalidation Message-ID: References: <20231117131816.24359-1-yi.l.liu@intel.com> <20231117131816.24359-2-yi.l.liu@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Dec 2023 02:28:42.0024 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: cd61511f-5548-4b3c-9a38-08dbfd158dfb X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF000252A4.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY8PR12MB7337 On Fri, Dec 15, 2023 at 01:50:07AM +0000, Tian, Kevin wrote: > > From: Liu, Yi L > > Sent: Thursday, December 14, 2023 7:27 PM > > > > On 2023/11/17 21:18, Yi Liu wrote:> This adds the data structure for > > flushing iotlb for the nested domain > > > > +struct iommu_hwpt_vtd_s1_invalidate { > > + __aligned_u64 addr; > > + __aligned_u64 npages; > > + __u32 flags; > > + __u32 __reserved; > > + __u32 error; > > + __u32 dev_id; > > +}; > > > > dev_id is used to report the failed device, userspace should be able to map > > it to a vRID, and inject it to VM as part of ITE/ICE error. > > > > However, I got a problem when trying to get dev_id in cache invalidation > > path, since this is filled in intel iommu driver. Seems like there is no > > good way for it. I've below alternatives to move forward, wish you have > > a look. > > > > - Reuse Nicolin's vRID->pRID mapping. If thevRID->pRID mapping is > > maintained, then intel iommu can report a vRID back to user. But intel > > iommu driver does not have viommu context, no place to hold the vRID- > > >pRID > > mapping. TBH. It may require other reasons to introduce it other than the > > error reporting need. Anyhow, this requires more thinking and also has > > dependency even if it is doable in intel side. > > this sounds like a cleaner way to inject knowledge which iommu driver > requires to find out the user tag. but yes it's a bit weird to introduce > viommu awareness in intel iommu driver when there is no such thing > in real hardware. I think a viommu is defined more like a software object representing the virtual IOMMU in a VM. Since VT-d has a vIOMMU in a nesting case, there could be an object for it too? > and for this error reporting case what we actually require is the > reverse map i.e. pRID->vRID. Not sure whether we can leverage the > same RID mapping uAPI as for ARM/AMD but ignore viommu_id > and then store vRID under device_domain_info. a bit tricky on > life cycle management and also incompatible with SIOV... One thing that I am not very clear here: since both vRID and dev_id are given by the VMM, shouldn't it already know the mapping if the point is to translate (pRID->)dev_id->vRID? Thanks Nicolin