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Fri, 15 Dec 2023 03:04:44 +0000 Received: from BN9PR11MB5276.namprd11.prod.outlook.com ([fe80::e7a4:a757:2f2e:f96a]) by BN9PR11MB5276.namprd11.prod.outlook.com ([fe80::e7a4:a757:2f2e:f96a%3]) with mapi id 15.20.7091.029; Fri, 15 Dec 2023 03:04:44 +0000 From: "Tian, Kevin" To: Nicolin Chen CC: "Liu, Yi L" , "joro@8bytes.org" , "alex.williamson@redhat.com" , "jgg@nvidia.com" , "robin.murphy@arm.com" , "baolu.lu@linux.intel.com" , "cohuck@redhat.com" , "eric.auger@redhat.com" , "kvm@vger.kernel.org" , "mjrosato@linux.ibm.com" , "chao.p.peng@linux.intel.com" , "yi.y.sun@linux.intel.com" , "peterx@redhat.com" , "jasowang@redhat.com" , "shameerali.kolothum.thodi@huawei.com" , "lulu@redhat.com" , "suravee.suthikulpanit@amd.com" , "iommu@lists.linux.dev" , "linux-kernel@vger.kernel.org" , "linux-kselftest@vger.kernel.org" , "Duan, Zhenzhong" , "joao.m.martins@oracle.com" , "Zeng, Xin" , "Zhao, Yan Y" Subject: RE: [PATCH v7 1/3] iommufd: Add data structure for Intel VT-d stage-1 cache invalidation Thread-Topic: [PATCH v7 1/3] iommufd: Add data structure for Intel VT-d stage-1 cache invalidation Thread-Index: AQHaGViOWXGe59nutU2rEx/0zRDvrrCozh6AgADg1VCAABsWAIAACKYA Date: Fri, 15 Dec 2023 03:04:44 +0000 Message-ID: References: <20231117131816.24359-1-yi.l.liu@intel.com> <20231117131816.24359-2-yi.l.liu@intel.com> In-Reply-To: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=intel.com; 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charset="us-ascii" Content-Transfer-Encoding: quoted-printable Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: BN9PR11MB5276.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 203547f1-4042-4605-f086-08dbfd1a970e X-MS-Exchange-CrossTenant-originalarrivaltime: 15 Dec 2023 03:04:44.8175 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: w8ZSgUJV7fu0SV87ho/yZHROlNixuPnrFvAJegnvvVzO3TPbxsrwKOCG52h9TtELrcu4Q3wN6sLFcaGDtxRwZQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: CYXPR11MB8753 X-OriginatorOrg: intel.com > From: Nicolin Chen > Sent: Friday, December 15, 2023 10:28 AM >=20 > On Fri, Dec 15, 2023 at 01:50:07AM +0000, Tian, Kevin wrote: > > > From: Liu, Yi L > > > Sent: Thursday, December 14, 2023 7:27 PM > > > > > > On 2023/11/17 21:18, Yi Liu wrote:> This adds the data structure for > > > flushing iotlb for the nested domain > > > > > > +struct iommu_hwpt_vtd_s1_invalidate { > > > + __aligned_u64 addr; > > > + __aligned_u64 npages; > > > + __u32 flags; > > > + __u32 __reserved; > > > + __u32 error; > > > + __u32 dev_id; > > > +}; > > > > > > dev_id is used to report the failed device, userspace should be able = to > map > > > it to a vRID, and inject it to VM as part of ITE/ICE error. > > > > > > However, I got a problem when trying to get dev_id in cache invalidat= ion > > > path, since this is filled in intel iommu driver. Seems like there is= no > > > good way for it. I've below alternatives to move forward, wish you ha= ve > > > a look. >=20 > > > > > > - Reuse Nicolin's vRID->pRID mapping. If thevRID->pRID mapping is > > > maintained, then intel iommu can report a vRID back to user. But inte= l > > > iommu driver does not have viommu context, no place to hold the vRID- > > > >pRID > > > mapping. TBH. It may require other reasons to introduce it other than= the > > > error reporting need. Anyhow, this requires more thinking and also ha= s > > > dependency even if it is doable in intel side. > > > > this sounds like a cleaner way to inject knowledge which iommu driver > > requires to find out the user tag. but yes it's a bit weird to introduc= e > > viommu awareness in intel iommu driver when there is no such thing > > in real hardware. >=20 > I think a viommu is defined more like a software object representing > the virtual IOMMU in a VM. Since VT-d has a vIOMMU in a nesting case, > there could be an object for it too? for VT-d it's not necessary to maintain such vIOMMU awareness in the kernel (before this error reporting case) given its interfaces are simply around hwpt's. there is no vIOMMU-scope operation provided by intel-iommu driver so far. >=20 > > and for this error reporting case what we actually require is the > > reverse map i.e. pRID->vRID. Not sure whether we can leverage the > > same RID mapping uAPI as for ARM/AMD but ignore viommu_id > > and then store vRID under device_domain_info. a bit tricky on > > life cycle management and also incompatible with SIOV... >=20 > One thing that I am not very clear here: since both vRID and dev_id > are given by the VMM, shouldn't it already know the mapping if the > point is to translate (pRID->)dev_id->vRID? >=20 it's true for current Qemu. but there is plan to support Qemu accepting a fd passed by Libvirt. In that case Qemu even doesn't see the sysfs path hence is not aware of pRID. otherwise yes we could leave the translation to VMM instead.