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Thu, 14 Dec 2023 19:32:42 -0800 Date: Thu, 14 Dec 2023 19:32:40 -0800 From: Nicolin Chen To: "Tian, Kevin" CC: "Liu, Yi L" , "joro@8bytes.org" , "alex.williamson@redhat.com" , "jgg@nvidia.com" , "robin.murphy@arm.com" , "baolu.lu@linux.intel.com" , "cohuck@redhat.com" , "eric.auger@redhat.com" , "kvm@vger.kernel.org" , "mjrosato@linux.ibm.com" , "chao.p.peng@linux.intel.com" , "yi.y.sun@linux.intel.com" , "peterx@redhat.com" , "jasowang@redhat.com" , "shameerali.kolothum.thodi@huawei.com" , "lulu@redhat.com" , "suravee.suthikulpanit@amd.com" , "iommu@lists.linux.dev" , "linux-kernel@vger.kernel.org" , "linux-kselftest@vger.kernel.org" , "Duan, Zhenzhong" , "joao.m.martins@oracle.com" , "Zeng, Xin" , "Zhao, Yan Y" Subject: Re: [PATCH v7 1/3] iommufd: Add data structure for Intel VT-d stage-1 cache invalidation Message-ID: References: <20231117131816.24359-1-yi.l.liu@intel.com> <20231117131816.24359-2-yi.l.liu@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Dec 2023 03:33:03.8161 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 925208fa-dd8e-40c7-8976-08dbfd1e8bd9 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: MN1PEPF0000F0E1.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN0PR12MB5836 On Fri, Dec 15, 2023 at 03:04:44AM +0000, Tian, Kevin wrote: > > From: Nicolin Chen > > Sent: Friday, December 15, 2023 10:28 AM > > On Fri, Dec 15, 2023 at 01:50:07AM +0000, Tian, Kevin wrote: > > > > From: Liu, Yi L > > > > Sent: Thursday, December 14, 2023 7:27 PM > > > > > > > > On 2023/11/17 21:18, Yi Liu wrote:> This adds the data structure for > > > > flushing iotlb for the nested domain > > > > > > > > +struct iommu_hwpt_vtd_s1_invalidate { > > > > + __aligned_u64 addr; > > > > + __aligned_u64 npages; > > > > + __u32 flags; > > > > + __u32 __reserved; > > > > + __u32 error; > > > > + __u32 dev_id; > > > > +}; > > > > > > > > dev_id is used to report the failed device, userspace should be able to > > map > > > > it to a vRID, and inject it to VM as part of ITE/ICE error. > > > and for this error reporting case what we actually require is the > > > reverse map i.e. pRID->vRID. Not sure whether we can leverage the > > > same RID mapping uAPI as for ARM/AMD but ignore viommu_id > > > and then store vRID under device_domain_info. a bit tricky on > > > life cycle management and also incompatible with SIOV... > > > > One thing that I am not very clear here: since both vRID and dev_id > > are given by the VMM, shouldn't it already know the mapping if the > > point is to translate (pRID->)dev_id->vRID? > > > > it's true for current Qemu. > > but there is plan to support Qemu accepting a fd passed by Libvirt. > In that case Qemu even doesn't see the sysfs path hence is not > aware of pRID. otherwise yes we could leave the translation to > VMM instead. I think I misread Yi's narrative: dev_id is a working approach for VMM to convert to a vRID, while he is asking for a better alternative :)