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Fri, 15 Dec 2023 05:52:41 GMT Received: from [10.201.3.91] (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Thu, 14 Dec 2023 21:52:34 -0800 Message-ID: <356c7a26-00eb-4189-b463-8946ac5e8201@quicinc.com> Date: Fri, 15 Dec 2023 11:22:32 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 07/10] dt-bindings: PCI: qcom: Add IPQ5332 SoC Content-Language: en-US To: Dmitry Baryshkov CC: , , , , , , , , , , , , , , , , , , , , , , , , , References: <20231214062847.2215542-1-quic_ipkumar@quicinc.com> <20231214062847.2215542-8-quic_ipkumar@quicinc.com> From: Praveenkumar I In-Reply-To: Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: y_9pkFcntguGdLcF8mnAq_eQCS_KVja0 X-Proofpoint-ORIG-GUID: y_9pkFcntguGdLcF8mnAq_eQCS_KVja0 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.997,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-12-09_01,2023-12-07_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 adultscore=0 spamscore=0 impostorscore=0 mlxscore=0 mlxlogscore=999 lowpriorityscore=0 bulkscore=0 suspectscore=0 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2311290000 definitions=main-2312150034 On 12/14/2023 12:45 PM, Dmitry Baryshkov wrote: > On Thu, 14 Dec 2023 at 08:30, Praveenkumar I wrote: >> Add support for the PCIe controller on the Qualcomm >> IPQ5332 SoC to the bindings. >> >> Signed-off-by: Praveenkumar I >> --- >> .../devicetree/bindings/pci/qcom,pcie.yaml | 36 +++++++++++++++++++ >> 1 file changed, 36 insertions(+) >> >> diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml >> index eadba38171e1..af5e67d2a984 100644 >> --- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml >> +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml >> @@ -21,6 +21,7 @@ properties: >> - qcom,pcie-apq8064 >> - qcom,pcie-apq8084 >> - qcom,pcie-ipq4019 >> + - qcom,pcie-ipq5332 >> - qcom,pcie-ipq6018 >> - qcom,pcie-ipq8064 >> - qcom,pcie-ipq8064-v2 >> @@ -170,6 +171,7 @@ allOf: >> compatible: >> contains: >> enum: >> + - qcom,pcie-ipq5332 >> - qcom,pcie-ipq6018 >> - qcom,pcie-ipq8074-gen3 >> then: >> @@ -332,6 +334,39 @@ allOf: >> - const: ahb # AHB reset >> - const: phy_ahb # PHY AHB reset >> >> + - if: >> + properties: >> + compatible: >> + contains: >> + enum: >> + - qcom,pcie-ipq5332 > As you seem to be depending on the ipq9574, could you please reuse the > DT entry too? Sure, will reuse ipq9574 entry. >> + then: >> + properties: >> + clocks: >> + minItems: 6 >> + maxItems: 6 >> + clock-names: >> + items: >> + - const: ahb # AHB clock >> + - const: aux # Auxiliary clock >> + - const: axi_m # AXI Master clock >> + - const: axi_s # AXI Slave clock >> + - const: axi_bridge # AXI bridge clock >> + - const: rchng >> + resets: >> + minItems: 8 >> + maxItems: 8 >> + reset-names: >> + items: >> + - const: pipe # PIPE reset >> + - const: sticky # Core sticky reset >> + - const: axi_m_sticky # AXI master sticky reset >> + - const: axi_m # AXI master reset >> + - const: axi_s_sticky # AXI slave sticky reset >> + - const: axi_s # AXI slave reset >> + - const: ahb # AHB reset >> + - const: aux # AUX reset >> + >> - if: >> properties: >> compatible: >> @@ -790,6 +825,7 @@ allOf: >> enum: >> - qcom,pcie-apq8064 >> - qcom,pcie-ipq4019 >> + - qcom,pcie-ipq5332 >> - qcom,pcie-ipq8064 >> - qcom,pcie-ipq8064v2 >> - qcom,pcie-ipq8074 >> -- >> 2.34.1 >> >> > -- Thanks, Praveenkumar