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From: Luo Jie <quic_luoj@quicinc.com>
To: <andrew@lunn.ch>, <davem@davemloft.net>, <edumazet@google.com>,
        <kuba@kernel.org>, <pabeni@redhat.com>, <robh+dt@kernel.org>,
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        <p.zabel@pengutronix.de>, <f.fainelli@gmail.com>
CC: <netdev@vger.kernel.org>, <devicetree@vger.kernel.org>,
        <linux-kernel@vger.kernel.org>, <linux-doc@vger.kernel.org>
Subject: [PATCH v8 00/14] add qca8084 ethernet phy driver
Date: Fri, 15 Dec 2023 15:39:50 +0800
Message-ID: <20231215074005.26976-1-quic_luoj@quicinc.com>
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QCA8084 is four-port PHY with maximum link capability 2.5G,
which supports the interface mode qusgmii and sgmii mode,
there are two PCSs available to connected with ethernet port.

QCA8084 can work in switch mode or PHY mode.
For switch mode, both PCS0 and PCS1 work on sgmii mode.
For PHY mode, PCS1 works on qusgmii mode.
The fourth PHY connected with PCS0 works on sgmii mode.

Besides this PHY driver patches, the PCS driver is also needed
to bring up the qca8084 device, which mainly configurs PCS
and clocks.

The qca8084 PHY driver depends on the following clock controller
patchset, the initial clocks and resets are provided by the clock
controller driver below.
https://lore.kernel.org/lkml/20231104034858.9159-2-quic_luoj@quicinc.com/T/

Changes in v3:
	* pick the two patches to introduce the interface mode
	  10g-qxgmii from Vladimir Oltean(olteanv@gmail.com).
	* add the function phydev_id_is_qca808x to identify the
	  PHY qca8081 and qca8084.
	* update the interface mode name PHY_INTERFACE_MODE_QUSGMII
	  to PHY_INTERFACE_MODE_10G_QXGMII.

Changes in v4:
	* remove the following patch:
	  <net: phylink: move phylink_pcs_neg_mode() to phylink.c>.
	* split out 10g_qxgmii change of ethernet-controller.yaml.

Changes in v5:
	* update the author of the patch below.
	  <introduce core support for phy-mode = "10g-qxgmii">.

Changes in v6:
	* drop the "inline" keyword.
	* apply the patches with "--max-line-length=80".

Changes in v7:
	* add possible interfaces of phydev
	* customize phy address
	* add initialized clock & reset config
	* add the work mode config
	* update qca,ar803x.yaml for the new added properties

Changes in v7:
	* updated the patcheset based on the latest code

Luo Jie (12):
  net: phy: at803x: add QCA8084 ethernet phy support
  net: phy: at803x: add the function phydev_id_is_qca808x
  net: phy: at803x: Add qca8084_config_init function
  net: phy: at803x: add qca8084_link_change_notify
  net: phy: at803x: add the possible_interfaces
  net: phy: at803x: add qca8084 switch registe access
  net: phy: at803x: set MDIO address of qca8084 PHY
  net: phy: at803x: parse qca8084 clocks and resets
  net: phy: at803x: add qca808x initial config sequence
  net: phy: at803x: configure qca8084 common clocks
  net: phy: at803x: configure qca8084 work mode
  dt-bindings: net: ar803x: add qca8084 PHY properties

Vladimir Oltean (2):
  net: phy: introduce core support for phy-mode = "10g-qxgmii"
  dt-bindings: net: ethernet-controller: add 10g-qxgmii mode

 .../bindings/net/ethernet-controller.yaml     |   1 +
 .../devicetree/bindings/net/qca,ar803x.yaml   | 158 ++++-
 Documentation/networking/phy.rst              |   6 +
 drivers/net/phy/at803x.c                      | 577 +++++++++++++++++-
 drivers/net/phy/phy-core.c                    |   1 +
 drivers/net/phy/phylink.c                     |  11 +-
 include/linux/phy.h                           |   4 +
 include/linux/phylink.h                       |   2 +
 8 files changed, 752 insertions(+), 8 deletions(-)


base-commit: 17cb8a20bde66a520a2ca7aad1063e1ce7382240
-- 
2.42.0