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bh=ErSPpkKKFAjMcXdmmaCZA2SpqYGJcA4cXAU/CRTyJxQ=; b=r0CAIC/YnzlhBnp1MNnSTcARYN0SDOOVWYPtxRCFDhVB2DYjDlZ5F/F//D/OUsRGcE e7oiHyzNUfKaAJPBEj8RG7k5XBmf7djD+DuxJMsOYLMva+rfiYX4WIWpjy81EyolUzhQ +ScYq2aKrLe34eviuc1+vXW9b+bglcIT1BbgupX27xen3W6ZGIpM5OpUCjtGVbeplbZe 14aPWHR5Yr5jg4HnMBsYlToTWpN/19dhMw+nJhJmvbIYgzDxaHUukzlqaiijU+7YcuC+ GbXbXNro7c6f87ZGRLTURS4ML70zpuk8n8v17Ikqutyb+u/ElYH1kPQwRCO1ZyyZ9VF8 dQGw== X-Gm-Message-State: AOJu0YyEyj7+3mY70CJigYyarXFEuUnq6aV9UgiLEKxWd5eULjD7cy56 ejTpJZrhwG3bEwAPXpC305Q6OQ== X-Received: by 2002:a17:906:fe4c:b0:a1c:4eee:3521 with SMTP id wz12-20020a170906fe4c00b00a1c4eee3521mr13916195ejb.56.1702628552522; Fri, 15 Dec 2023 00:22:32 -0800 (PST) Received: from [192.168.1.20] ([178.197.218.27]) by smtp.gmail.com with ESMTPSA id ry9-20020a1709068d8900b009adc77fe164sm10493875ejc.66.2023.12.15.00.22.30 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 15 Dec 2023 00:22:32 -0800 (PST) Message-ID: Date: Fri, 15 Dec 2023 09:22:30 +0100 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v8 14/14] dt-bindings: net: ar803x: add qca8084 PHY properties Content-Language: en-US To: Luo Jie , andrew@lunn.ch, davem@davemloft.net, edumazet@google.com, kuba@kernel.org, pabeni@redhat.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, hkallweit1@gmail.com, linux@armlinux.org.uk, corbet@lwn.net, p.zabel@pengutronix.de, f.fainelli@gmail.com Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org References: <20231215074005.26976-1-quic_luoj@quicinc.com> <20231215074005.26976-15-quic_luoj@quicinc.com> From: Krzysztof Kozlowski Autocrypt: addr=krzysztof.kozlowski@linaro.org; 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charset=UTF-8 Content-Transfer-Encoding: 7bit On 15/12/2023 08:40, Luo Jie wrote: > The following properties are added for qca8084 PHY. > > 1. add the compatible string "ethernet-phy-id004d.d180" since > the PHY device is not accessible during MDIO bus register. > 2. add property "qcom,phy-addr-fixup" for customizing MDIO address. > 3. add property "qcom,phy-work-mode" for specifying qca8084 PHY > work mode. > 4. add the initial clocks and resets. All my previous comments (sent one minute before this patchset :) ) apply. Please respond to them or implement them in v5 (not earlier than after 24h). Best regards, Krzysztof