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[2604:1380:45e3:2400::1]) by mx.google.com with ESMTPS id pl17-20020a17090b269100b002869d1b1921si13468953pjb.31.2023.12.15.02.56.16 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 15 Dec 2023 02:56:16 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel+bounces-787-linux.lists.archive=gmail.com@vger.kernel.org designates 2604:1380:45e3:2400::1 as permitted sender) client-ip=2604:1380:45e3:2400::1; Authentication-Results: mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=4jH4uR7W; dkim=neutral (no key) header.i=@linutronix.de; spf=pass (google.com: domain of linux-kernel+bounces-787-linux.lists.archive=gmail.com@vger.kernel.org designates 2604:1380:45e3:2400::1 as permitted sender) smtp.mailfrom="linux-kernel+bounces-787-linux.lists.archive=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from smtp.subspace.kernel.org (wormhole.subspace.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by sv.mirrors.kernel.org (Postfix) with ESMTPS id B250628597D for ; Fri, 15 Dec 2023 10:56:15 +0000 (UTC) Received: from localhost.localdomain (localhost.localdomain [127.0.0.1]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 3CB431C2BD; Fri, 15 Dec 2023 10:56:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="4jH4uR7W"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="jEgtJWt9" X-Original-To: linux-kernel@vger.kernel.org Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 784591A729; Fri, 15 Dec 2023 10:56:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de From: Thomas Gleixner DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1702637763; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: in-reply-to:in-reply-to:references:references; bh=AcJ8sEUJ5wj/9ROjAHSdD4NZ0BJCgYAH/QnOMV8p1BM=; b=4jH4uR7WEkvi3q9xmp3Pnfz/VZdVGzqrC2Ng0CQcqzJH+ptjFz5IOlXJ2cY3R0E8m02USo nWZvqcwY6YYDlpWLFfgGxvn4oZ+Qd532l8y8O7JrR/41lk7o/Psa0XhKWVCeI5pnvTGKB9 VpUuZLvJlWw6dl4jQuGRqzQQikTGtt7bGTky50xZbdP/4lmgTMQCvvCdFs4q5YGAM6Hkqm BwBNsvrL/Q4/sMKASPFoikKwsPcRyLEcVQpb0yljADrCeihjHwQYoZOi+BqLdSWZ48fVAd rLDRi+LNSxHFLn28JcPrF4XSmJNYPsd5cDjWMeTI8NKuAYyR2O+C3QonbxTYAw== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1702637763; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: in-reply-to:in-reply-to:references:references; bh=AcJ8sEUJ5wj/9ROjAHSdD4NZ0BJCgYAH/QnOMV8p1BM=; b=jEgtJWt9e5Q0raTT/BlFzFleI+L8MrVj3EijjrRxmXWwtx4MX49POCfWHUlSiTmLEOxbGC CmtpR1Dee3bgPbDQ== To: Serge Semin Cc: Linus Walleij , Luo Jiaxing , Marc Zyngier , Bartosz Golaszewski , Serge Semin , Andy Shevchenko , Andy Shevchenko , "open list:GPIO SUBSYSTEM" , "linux-kernel@vger.kernel.org" , Linuxarm Subject: Re: [PATCH v1] gpio: dwapb: mask/unmask IRQ when disable/enable it In-Reply-To: References: <1606728979-44259-1-git-send-email-luojiaxing@huawei.com> <87fs03opju.ffs@tglx> Date: Fri, 15 Dec 2023 11:56:02 +0100 Message-ID: <87a5qbohtp.ffs@tglx> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain On Fri, Dec 15 2023 at 13:24, Serge Semin wrote: > On Fri, Dec 15, 2023 at 09:09:09AM +0100, Thomas Gleixner wrote: >> On Sat, Dec 05 2020 at 22:58, Linus Walleij wrote: >> > Sorry for top posting but I need the help of the irqchip maintainer >> > Marc Z to hash this out. >> > >> > The mask/unmask/disable/enable semantics is something that >> > you need to work with every day to understand right. >> >> The patch is correct. >> >> The irq_enable() callback is required to be a superset of >> irq_unmask(). I.e. the core code expects it to do: >> >> 1) Some preparatory work to enable the interrupt line >> >> 2) Unmask the interrupt, which is why the masked state is cleared >> by the core after invoking the irq_enable() callback. >> >> #2 is pretty obvious because if an interrupt chip does not implement the >> irq_enable() callback the core defaults to irq_unmask() >> >> Correspondingly the core expects from the irq_disable() callback: >> >> 1) To mask the interrupt >> >> 2) To do some extra work to disable the interrupt line >> >> Same reasoning as above vs. #1 as the core fallback is to invoke the >> irq_unmask() callback when the irq_disable() callback is not >> implemented. > > Just curious. Wouldn't that be more correct/portable for the core to > call both callbacks when it's required and if both are provided? So > the supersetness requirement would be no longer applied to the > IRQ enable/disable callbacks implementation thus avoiding the code > duplications in the low-level drivers. We could do that, but there are chips which require atomicity of the operations (#1/#2). Not sure whether it safes much. Thanks, tglx