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[2604:1380:45e3:2400::1]) by mx.google.com with ESMTPS id x12-20020a17090abc8c00b0028b1b340554si2218723pjr.166.2023.12.15.08.22.05 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 15 Dec 2023 08:22:05 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel+bounces-1284-linux.lists.archive=gmail.com@vger.kernel.org designates 2604:1380:45e3:2400::1 as permitted sender) client-ip=2604:1380:45e3:2400::1; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel+bounces-1284-linux.lists.archive=gmail.com@vger.kernel.org designates 2604:1380:45e3:2400::1 as permitted sender) smtp.mailfrom="linux-kernel+bounces-1284-linux.lists.archive=gmail.com@vger.kernel.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Received: from smtp.subspace.kernel.org (wormhole.subspace.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by sv.mirrors.kernel.org (Postfix) with ESMTPS id 23445282D9D for ; Fri, 15 Dec 2023 16:22:05 +0000 (UTC) Received: from localhost.localdomain (localhost.localdomain [127.0.0.1]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 9A8CF3C466; Fri, 15 Dec 2023 16:21:58 +0000 (UTC) X-Original-To: linux-kernel@vger.kernel.org Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id A0EAE3BB25; Fri, 15 Dec 2023 16:21:55 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 5D2BFC15; Fri, 15 Dec 2023 08:22:40 -0800 (PST) Received: from FVFF77S0Q05N (unknown [10.57.45.203]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 1150B3F5A1; Fri, 15 Dec 2023 08:21:52 -0800 (PST) Date: Fri, 15 Dec 2023 16:21:45 +0000 From: Mark Rutland To: James Clark Cc: linux-arm-kernel@lists.infradead.org, linux-perf-users@vger.kernel.org, linux-next@vger.kernel.org, will@kernel.org, u.kleine-koenig@pengutronix.de, Nathan Chancellor , Nick Desaulniers , Bill Wendling , Justin Stitt , Anshuman Khandual , Suzuki K Poulose , linux-kernel@vger.kernel.org, llvm@lists.linux.dev Subject: Re: [PATCH 1/2] arm: perf: Fix ARCH=arm build with GCC in armv8pmu_write_evtype() Message-ID: References: <20231215150040.3342183-1-james.clark@arm.com> <20231215150040.3342183-2-james.clark@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20231215150040.3342183-2-james.clark@arm.com> On Fri, Dec 15, 2023 at 03:00:38PM +0000, James Clark wrote: > LLVM ignores everything inside the if statement and doesn't generate > errors, but GCC doesn't ignore it, resulting in the following error: > > drivers/perf/arm_pmuv3.c: In function 'armv8pmu_write_evtype': > include/linux/bits.h:34:29: error: left shift count >= width of type [-Werror=shift-count-overflow] > 34 | (((~UL(0)) - (UL(1) << (l)) + 1) & \ > > Fix it by changing the if to #if. I reckon it'd be cleaner to use GENMASK_ULL for the TH and TC fields, in include/linux/perf/arm_pmu.h have: | /* | * PMXEVTYPER: Event selection reg | */ | #define ARMV8_PMU_EVTYPE_EVENT GENMASK(15, 0) /* Mask for EVENT bits */ | #define ARMV8_PMU_EVTYPE_TH GENMASK_ULL(43, 32) /* arm64 only */ | #define ARMV8_PMU_EVTYPE_TC GENMASK_ULL(63, 61) /* arm64 only */ IIUC that should silence this warning, and it'd remove the need for the ifdeffery and other changes in patch 2. Does that work, or am I missing something? Thanks, Mark. > > Fixes: 3115ee021bfb ("arm64: perf: Include threshold control fields in PMEVTYPER mask") > Reported-by: Uwe Kleine-K"onig > Closes: https://lore.kernel.org/linux-arm-kernel/20231215120817.h2f3akgv72zhrtqo@pengutronix.de/ > Signed-off-by: James Clark > --- > drivers/perf/arm_pmuv3.c | 5 +++-- > 1 file changed, 3 insertions(+), 2 deletions(-) > > diff --git a/drivers/perf/arm_pmuv3.c b/drivers/perf/arm_pmuv3.c > index 23fa6c5da82c..3ed2086cefc3 100644 > --- a/drivers/perf/arm_pmuv3.c > +++ b/drivers/perf/arm_pmuv3.c > @@ -631,8 +631,9 @@ static void armv8pmu_write_evtype(int idx, unsigned long val) > ARMV8_PMU_EXCLUDE_EL0 | > ARMV8_PMU_EXCLUDE_EL1; > > - if (IS_ENABLED(CONFIG_ARM64)) > - mask |= ARMV8_PMU_EVTYPE_TC | ARMV8_PMU_EVTYPE_TH; > +#if IS_ENABLED(CONFIG_ARM64) > + mask |= ARMV8_PMU_EVTYPE_TC | ARMV8_PMU_EVTYPE_TH; > +#endif > > val &= mask; > write_pmevtypern(counter, val); > -- > 2.34.1 >