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Fri, 15 Dec 2023 11:13:07 -0800 From: Emil Renner Berthing In-Reply-To: References: <20231130151932.729708-1-emil.renner.berthing@canonical.com> <20231213-jester-rendering-dd876ef8e8ac@spud> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 Date: Fri, 15 Dec 2023 11:13:07 -0800 Message-ID: Subject: Re: (subset) [PATCH v2 0/8] Add JH7100 errata and update device tree To: Geert Uytterhoeven , Conor Dooley Cc: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Emil Renner Berthing , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Emil Renner Berthing , Rob Herring , Krzysztof Kozlowski , Cristian Ciocaltea Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Geert Uytterhoeven wrote: > Hi Conor, > > On Wed, Dec 13, 2023 at 4:43=E2=80=AFPM Conor Dooley w= rote: > > From: Conor Dooley > > > > On Thu, 30 Nov 2023 16:19:24 +0100, Emil Renner Berthing wrote: > > > Now that the driver for the SiFive cache controller supports manual > > > flushing as non-standard cache operations[1] we can add an errata opt= ion > > > for the StarFive JH7100 SoC and update the device tree with the cache > > > controller, dedicated DMA pool and add MMC nodes for the SD-card and > > > wifi. > > > > > > This series needs the following commit in [1] to work properly: > > > > > > [...] > > > > Applied to riscv-cache-for-next, thanks! > > > > [1/8] riscv: errata: Add StarFive JH7100 errata > > https://git.kernel.org/conor/c/64fc984a8a54 > > That's the one which also needs depends on !DMA_DIRECT_REMAP? Yes, thanks. I sent a fix now: https://lore.kernel.org/linux-riscv/20231215190909.3722757-1-emil.renner.be= rthing@canonical.com/ /Emil