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Date: Sat, 16 Dec 2023 18:17:30 +0100
From: Andrew Lunn <andrew@lunn.ch>
To: Jie Luo <quic_luoj@quicinc.com>
Cc: "Russell King (Oracle)" <linux@armlinux.org.uk>,
	Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>,
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	linux-doc@vger.kernel.org
Subject: Re: [PATCH v8 14/14] dt-bindings: net: ar803x: add qca8084 PHY
 properties
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In-Reply-To: <3a40570b-40bf-4609-b1f4-a0a6974accea@quicinc.com>

> Yes, Russell, i will add an example in the DT doc in the next patch set.
> The following is the device node used for the current qca8084 PHY
> code design.

If you look at Christians work, this would be expressed differently:

> mdio: mdio@90000 {
>     ethernet-phy-package@1 {
> 
>         compatible = "qca,qca8084-package";
> 
>         qcom,phy-work-mode = <2>;
>         clocks = <&qca8k_nsscc NSS_CC_APB_BRIDGE_CLK>,
>                <&qca8k_nsscc NSS_CC_AHB_CLK>,
>                <&qca8k_nsscc NSS_CC_SEC_CTRL_AHB_CLK>,
>                <&qca8k_nsscc NSS_CC_TLMM_CLK>,
>                <&qca8k_nsscc NSS_CC_TLMM_AHB_CLK>,
>                <&qca8k_nsscc NSS_CC_CNOC_AHB_CLK>,
>                <&qca8k_nsscc NSS_CC_MDIO_AHB_CLK>,
>                <&qca8k_nsscc NSS_CC_MDIO_MASTER_AHB_CLK>,
>                <&qca8k_nsscc NSS_CC_SRDS0_SYS_CLK>,
>                <&qca8k_nsscc NSS_CC_SRDS1_SYS_CLK>;
>         clock-names = "apb_bridge",
>                 "ahb",
>                 "sec_ctrl_ahb",
>                 "tlmm",
>                 "tlmm_ahb",
>                 "cnoc_ahb",
>                 "mdio_ahb",
>                 "mdio_master_ahb",
>                 "srds0_sys",
>                 "srds1_sys";
>         resets = <&qca8k_nsscc NSS_CC_SRDS0_SYS_ARES>,
>                <&qca8k_nsscc NSS_CC_SRDS1_SYS_ARES>,
>                <&qca8k_nsscc NSS_CC_DSP_ARES>;
>         reset-names = "srds0_sys",
>                       "srds1_sys";
>

All the properties above are common to the package as a whole.

Then follow the four individual PHYs, and the properties which are
specific to each one.

> 
>         ethernet-phy@0 {
>             compatible = "ethernet-phy-id004d.d180";
>             reg = <0>;
>             clocks = <qca8k_nsscc NSS_CC_GEPHY0_SYS_CLK>,
>             clock-names = <"gephy_sys">;
>             resets = <&qca8k_nsscc NSS_CC_GEPHY0_SYS_ARES>,
>                      <&qca8k_nsscc NSS_CC_GEPHY0_ARES>;
>             reset-names = "gephy_sys", "gephy_soft";
>         };
>     
>     
>         ethernet-phy@1 {
>             compatible = "ethernet-phy-id004d.d180";
>             reg = <1>;
>             clocks = <qca8k_nsscc NSS_CC_GEPHY1_SYS_CLK>,
>             clock-names = <"gephy_sys">;
>             resets = <&qca8k_nsscc NSS_CC_GEPHY1_SYS_ARES>,
>                      <&qca8k_nsscc NSS_CC_GEPHY1_ARES>;
>             reset-names = "gephy_sys", "gephy_soft";
>     
>         };
>     
>         ethernet-phy@2 {
>             compatible = "ethernet-phy-id004d.d180";
>             reg = <2>;
>             clocks = <qca8k_nsscc NSS_CC_GEPHY2_SYS_CLK>,
>             clock-names = <"gephy_sys">;
>             resets = <&qca8k_nsscc NSS_CC_GEPHY2_SYS_ARES>,
>                      <&qca8k_nsscc NSS_CC_GEPHY2_ARES>;
>             reset-names = "gephy_sys", "gephy_soft";
>     
>         };
>     
>         ethernet-phy@3 {
>             compatible = "ethernet-phy-id004d.d180";
>             reg = <3>;
>             clocks = <qca8k_nsscc NSS_CC_GEPHY3_SYS_CLK>,
>             clock-names = <"gephy_sys">;
>             reset-names = "gephy_sys", "gephy_soft";
>         };
> };

	Andrew