Received-SPF: pass (google.com: domain of linux-kernel+bounces-2294-linux.lists.archive=gmail.com@vger.kernel.org designates 147.75.199.223 as permitted sender) client-ip=147.75.199.223;
Date: Sat, 16 Dec 2023 18:30:00 +0100
From: Andrew Lunn <andrew@lunn.ch>
To: Jie Luo <quic_luoj@quicinc.com>
Cc: davem@davemloft.net, edumazet@google.com, kuba@kernel.org,
	pabeni@redhat.com, robh+dt@kernel.org,
	krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org,
	hkallweit1@gmail.com, linux@armlinux.org.uk, corbet@lwn.net,
	p.zabel@pengutronix.de, f.fainelli@gmail.com,
	netdev@vger.kernel.org, devicetree@vger.kernel.org,
	linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org
Subject: Re: [PATCH v8 14/14] dt-bindings: net: ar803x: add qca8084 PHY
 properties
Message-ID: <15d95222-35dd-4ea1-a1a3-3ad9e4ef0349@lunn.ch>
References: <20231215074005.26976-1-quic_luoj@quicinc.com>
 <20231215074005.26976-15-quic_luoj@quicinc.com>
 <60b9081c-76fa-4122-b7ae-5c3dcf7229f9@lunn.ch>
 <a65ad12d-b990-4439-b196-903f4a5f096a@quicinc.com>
 <f5c5cbce-c36e-498a-97e2-35f06d927d74@lunn.ch>
 <a9798333-3105-422f-8033-76c0b1d4f439@quicinc.com>
Precedence: bulk
MIME-Version: 1.0
Content-Type: text/plain; charset=us-ascii
Content-Disposition: inline
In-Reply-To: <a9798333-3105-422f-8033-76c0b1d4f439@quicinc.com>

> The following is the chip package, the chip can work on the switch mode
> like the existed upstream code qca8k, where PHY1-PHY4 is connected with
> MAC1-MAC4 directly; The chip can also work on the PHY mode, where PHY1-
> PHY4 is connected with PCS1 by 10g-qxgmii; Either switch mode or PHY mode,
> the PHY4 is optionally connected with PCS0 by SGMII, PCS0 and PCS1
> are connected with the SoC(IPQ platform) PCSes.

I don't really understand. Are you saying the hardware is actually :


+----------------------------------------------+
|          PCS1           PCS0                 |
|                                              |
|          MAC0           MAC5                 |
|           |              |                   |
|     +-----+--------------+-------------+     |
|     |                                  |     |
|     |                Switch            |     |
|     |                                  |     |
|     +-+---------+---------+---------+--+     |
|       |         |         |         |        |
|      MAC1      MAC2      MAC3      MAC4      |
|                                              |
|      PHY1      PHY2      PHY3      PHY4      |
+----------------------------------------------+

When in PHY mode, the switch is hard coded to map the 4 PCS1 channels
straight to MAC1-MAC4 and all switch functionality is disabled. But
then in switch mode, the switch can be controlled as a DSA switch? The
10G PCS1 is then a single 10G port, not 4x 2.5G?

Is there a product brief for this PHY? That might help us understand
this hardware?

    Andrew