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Sat, 16 Dec 2023 10:49:10 -0800 Date: Sat, 16 Dec 2023 10:49:08 -0800 From: Nicolin Chen To: Yi Liu CC: "Tian, Kevin" , "joro@8bytes.org" , "alex.williamson@redhat.com" , "jgg@nvidia.com" , "robin.murphy@arm.com" , "baolu.lu@linux.intel.com" , "cohuck@redhat.com" , "eric.auger@redhat.com" , "kvm@vger.kernel.org" , "mjrosato@linux.ibm.com" , "chao.p.peng@linux.intel.com" , "yi.y.sun@linux.intel.com" , "peterx@redhat.com" , "jasowang@redhat.com" , "shameerali.kolothum.thodi@huawei.com" , "lulu@redhat.com" , "suravee.suthikulpanit@amd.com" , "iommu@lists.linux.dev" , "linux-kernel@vger.kernel.org" , "linux-kselftest@vger.kernel.org" , "Duan, Zhenzhong" , "joao.m.martins@oracle.com" , "Zeng, Xin" , "Zhao, Yan Y" Subject: Re: [PATCH v7 1/3] iommufd: Add data structure for Intel VT-d stage-1 cache invalidation Message-ID: References: <20231117131816.24359-1-yi.l.liu@intel.com> <20231117131816.24359-2-yi.l.liu@intel.com> <7c398efc-8a2f-479d-bcff-ded8cc1ef3d0@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Dec 2023 18:49:24.5406 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 0d9ff39c-5ca6-4dd2-2270-08dbfe67b948 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF00026367.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW3PR12MB4428 On Fri, Dec 15, 2023 at 12:01:19PM +0800, Yi Liu wrote: > On 2023/12/15 11:32, Nicolin Chen wrote: > > On Fri, Dec 15, 2023 at 03:04:44AM +0000, Tian, Kevin wrote: > > > > From: Nicolin Chen > > > > Sent: Friday, December 15, 2023 10:28 AM > > > > On Fri, Dec 15, 2023 at 01:50:07AM +0000, Tian, Kevin wrote: > > > > > > From: Liu, Yi L > > > > > > Sent: Thursday, December 14, 2023 7:27 PM > > > > > > > > > > > > On 2023/11/17 21:18, Yi Liu wrote: > > > > > and for this error reporting case what we actually require is the > > > > > reverse map i.e. pRID->vRID. Not sure whether we can leverage the > > > > > same RID mapping uAPI as for ARM/AMD but ignore viommu_id > > > > > and then store vRID under device_domain_info. a bit tricky on > > > > > life cycle management and also incompatible with SIOV... > > > > > > > > One thing that I am not very clear here: since both vRID and dev_id > > > > are given by the VMM, shouldn't it already know the mapping if the > > > > point is to translate (pRID->)dev_id->vRID? > > > > > > > > > > it's true for current Qemu. > > > > > > but there is plan to support Qemu accepting a fd passed by Libvirt. > > > In that case Qemu even doesn't see the sysfs path hence is not > > > aware of pRID. otherwise yes we could leave the translation to > > > VMM instead. > > > > I think I misread Yi's narrative: dev_id is a working approach > > for VMM to convert to a vRID, while he is asking for a better > > alternative :) > > In concept, dev_id works, but in reality we have problem to get a dev_id > for a given device in intel iommu driver, hence I'm asking for help here. :) Yea, I got that. Would it be possible for us to postpone this error report in the vtd driver? Jason is taking vacation, so he'll unlikely be very active until the new year, although he would probably spare some time taking the cache_invalidate series once it's mature. If the final solution is to use pRID<->vRID mappings for vtd too, we'd likely need the viommu/dev_set_virtual_id series that I am still working on, which certainly won't make it to this cycle. Thanks Nic