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From: Atish Kumar Patra <atishp@rivosinc.com>
Date: Sat, 16 Dec 2023 15:54:06 -0800
Message-ID: <CAHBxVyGs0kry-d1jcKWmR_AXm41hrUuvXAZxk+ht-AXS28mZqA@mail.gmail.com>
Subject: Re: [RFC 4/9] drivers/perf: riscv: Read upper bits of a firmware counter
To: Anup Patel <anup@brainfault.org>
Cc: Conor Dooley <conor.dooley@microchip.com>, linux-kernel@vger.kernel.org, 
	Alexandre Ghiti <alexghiti@rivosinc.com>, Andrew Jones <ajones@ventanamicro.com>, 
	Atish Patra <atishp@atishpatra.org>, Guo Ren <guoren@kernel.org>, 
	Icenowy Zheng <uwu@icenowy.me>, kvm-riscv@lists.infradead.org, kvm@vger.kernel.org, 
	linux-riscv@lists.infradead.org, Mark Rutland <mark.rutland@arm.com>, 
	Palmer Dabbelt <palmer@dabbelt.com>, Paul Walmsley <paul.walmsley@sifive.com>, 
	Will Deacon <will@kernel.org>
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On Thu, Dec 14, 2023 at 4:30=E2=80=AFAM Anup Patel <anup@brainfault.org> wr=
ote:
>
> On Thu, Dec 7, 2023 at 6:03=E2=80=AFPM Conor Dooley <conor.dooley@microch=
ip.com> wrote:
> >
> > On Mon, Dec 04, 2023 at 06:43:05PM -0800, Atish Patra wrote:
> > > SBI v2.0 introduced a explicit function to read the upper bits
> > > for any firmwar counter width that is longer than XLEN. Currently,
> > > this is only applicable for RV32 where firmware counter can be
> > > 64 bit.
> >
> > The v2.0 spec explicitly says that this function returns the upper
> > 32 bits of the counter for rv32 and will always return 0 for rv64
> > or higher. The commit message here seems overly generic compared to
> > the actual definition in the spec, and makes it seem like it could
> > be used with a 128 bit counter on rv64 to get the upper 64 bits.
> >
> > I tried to think about what "generic" situation the commit message
> > had been written for, but the things I came up with would all require
> > changes to the spec to define behaviour for FID #5 and/or FID #1, so
> > in the end I couldn't figure out the rationale behind the non-committal
> > wording used here.
> >
The intention was to show that this can be extended in the future for
other XLEN systems
(obviously with spec modification). But I got your point. We can
update it whenever we have
such systems and the spec. Modified the commit text to match what is
in the spec .

> > >
> > > Signed-off-by: Atish Patra <atishp@rivosinc.com>
> > > ---
> > >  drivers/perf/riscv_pmu_sbi.c | 11 +++++++++--
> > >  1 file changed, 9 insertions(+), 2 deletions(-)
> > >
> > > diff --git a/drivers/perf/riscv_pmu_sbi.c b/drivers/perf/riscv_pmu_sb=
i.c
> > > index 40a335350d08..1c9049e6b574 100644
> > > --- a/drivers/perf/riscv_pmu_sbi.c
> > > +++ b/drivers/perf/riscv_pmu_sbi.c
> > > @@ -490,16 +490,23 @@ static u64 pmu_sbi_ctr_read(struct perf_event *=
event)
> > >       struct hw_perf_event *hwc =3D &event->hw;
> > >       int idx =3D hwc->idx;
> > >       struct sbiret ret;
> > > -     union sbi_pmu_ctr_info info;
> > >       u64 val =3D 0;
> > > +     union sbi_pmu_ctr_info info =3D pmu_ctr_list[idx];
> > >
> > >       if (pmu_sbi_is_fw_event(event)) {
> > >               ret =3D sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_FW_R=
EAD,
> > >                               hwc->idx, 0, 0, 0, 0, 0);
> > >               if (!ret.error)
> > >                       val =3D ret.value;
> > > +#if defined(CONFIG_32BIT)
> >
> > Why is this not IS_ENABLED()? The code below uses one. You could then
> > fold it into the if statement below.
> >

Done.

> > > +             if (sbi_v2_available && info.width >=3D 32) {
> >
> >  >=3D 32? I know it is from the spec, but why does the spec define it a=
s
> >  "One less than number of bits in CSR"? Saving bits in the structure I
> >  guess?
>
> Yes, it is for using fewer bits in counter_info.
>
> The maximum width of a HW counter is 64 bits. The absolute value 64
> requires 7 bits in counter_info whereas absolute value 63 requires 6 bits
> in counter_info. Also, a HW counter if it exists will have at least 1 bit
> implemented otherwise the HW counter does not exist.
>
> Regards,
> Anup
>
> >
> > > +                     ret =3D sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUN=
TER_FW_READ_HI,
> > > +                                     hwc->idx, 0, 0, 0, 0, 0);
> >
> > > +                     if (!ret.error)
> > > +                             val =3D val | ((u64)ret.value << 32);
> >
> > If the first ecall fails but the second one doesn't won't we corrupt
> > val by only setting the upper bits? If returning val =3D=3D 0 is the th=
ing
> > to do in the error case (which it is in the existing code) should the
> > first `if (!ret.error)` become `if (ret.error)` -> `return 0`?
> >

Sure. Fixed it.

> >
> > > +                             val =3D val | ((u64)ret.value << 32);
> >
> > Also, |=3D ?
> >

Done.


> > Cheers,
> > Conor.
> >
> > > +             }
> > > +#endif
> > >       } else {
> > > -             info =3D pmu_ctr_list[idx];
> > >               val =3D riscv_pmu_ctr_read_csr(info.csr);
> > >               if (IS_ENABLED(CONFIG_32BIT))
> > >                       val =3D ((u64)riscv_pmu_ctr_read_csr(info.csr +=
 0x80)) << 31 | val;
> > > --
> > > 2.34.1
> > >