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Date: Mon, 18 Dec 2023 00:23:30 -0500
From: Abdel Alkuor <alkuor@gmail.com>
To: Guenter Roeck <linux@roeck-us.net>
Cc: Jean Delvare <jdelvare@suse.com>, Rob Herring <robh+dt@kernel.org>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
	Conor Dooley <conor+dt@kernel.org>,
	Jonathan Corbet <corbet@lwn.net>, linux-hwmon@vger.kernel.org,
	devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
	linux-doc@vger.kernel.org
Subject: Re: [PATCH 2/2] hwmon: Add AMS AS6200 temperature sensor
Message-ID: <ZX/XUpHl+5ZiAcou@abdel>
References: <149032e99136a9fe47c3533b57a71092646e497d.1702744180.git.alkuor@gmail.com>
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 <aa93010a-7ab0-4b9d-bb5d-25ea15b81120@roeck-us.net>
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 <c606c40b-8571-4618-827a-555ceab3ae74@roeck-us.net>
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On Sat, Dec 16, 2023 at 10:06:03PM -0800, Guenter Roeck wrote:
> On 12/16/23 20:59, Abdel Alkuor wrote:
> > On Sat, Dec 16, 2023 at 05:40:35PM -0800, Guenter Roeck wrote:
> > > On 12/16/23 14:07, Abdel Alkuor wrote:
> > > > On Sat, Dec 16, 2023 at 10:46:53AM -0800, Guenter Roeck wrote:
> > > > > On 12/16/23 08:39, Abdel Alkuor wrote:
> >       ...
> >     }
> > 
> > Based on that, the new tmp112 set_mask and clr_mask would look like this instead,
> >    [tmp112] = {
> >    	.set_mask = 3 << 6,	/* 8 samples / second */
> >    	.clr_mask = 1 << 15,	/* no one-shot mode*/
> > 	.config_reg_16bits = 1,
> >    	...
> >    }
> > 
> 
> Yes, you are correct, we'll need something like that. lm75_update_interval()
> tries to solve the problem for tmp112, but that doesn't work with
> set_mask/clear_mask. We should have a separate function lm75_read_config(),
> though, to hide the complexity.
>
I'll fix tmp112 parameters in another patch as as6200 patch 2 in v2
implements 2bytes read/write for the configure reg.
https://marc.info/?l=linux-hwmon&m=170287522119545&w=2

On another note, I checked all the supported chips in lm75 to see
which ones support an alert bit, only 3 chips support it; tmp112(bit 5 in the second byte),
tmp100, and tmp101 (bit 7 in the first byte).

Thanks,
Abdel