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Date: Mon, 18 Dec 2023 10:34:09 +0100
From: Andrew Lunn <andrew@lunn.ch>
To: Jie Luo <quic_luoj@quicinc.com>
Cc: "Russell King (Oracle)" <linux@armlinux.org.uk>,
	Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>,
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	linux-doc@vger.kernel.org
Subject: Re: [PATCH v8 14/14] dt-bindings: net: ar803x: add qca8084 PHY
 properties
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> Thanks Andrew for the proposal.
> For the pure PHY chip qca8084, there is no driver to parse the package
> level device tree node for common clocks and resets.

So you still have not look at the work Christian is doing. You must
work together with Christian. This driver is not going to be accepted
unless you do.

> > >          ethernet-phy@0 {
> > >              compatible = "ethernet-phy-id004d.d180";
> > >              reg = <0>;
> > >              clocks = <qca8k_nsscc NSS_CC_GEPHY0_SYS_CLK>,
> > >              clock-names = <"gephy_sys">;
> > >              resets = <&qca8k_nsscc NSS_CC_GEPHY0_SYS_ARES>,
> > >                       <&qca8k_nsscc NSS_CC_GEPHY0_ARES>;
> > >              reset-names = "gephy_sys", "gephy_soft";

Which of these properties exist for the Pure PHY device? Which exist
for the integrated switch? And by that, i mean which are actual pins
on the PHY device? We need the device tree binding to list which
properties are required for each use case.

	   Andrew