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[2604:1380:40f1:3f00::1]) by mx.google.com with ESMTPS id v33-20020a631521000000b005c5e214d722si17643847pgl.80.2023.12.18.02.49.14 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 Dec 2023 02:49:14 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel+bounces-3364-linux.lists.archive=gmail.com@vger.kernel.org designates 2604:1380:40f1:3f00::1 as permitted sender) client-ip=2604:1380:40f1:3f00::1; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel+bounces-3364-linux.lists.archive=gmail.com@vger.kernel.org designates 2604:1380:40f1:3f00::1 as permitted sender) smtp.mailfrom="linux-kernel+bounces-3364-linux.lists.archive=gmail.com@vger.kernel.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Received: from smtp.subspace.kernel.org (wormhole.subspace.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by sy.mirrors.kernel.org (Postfix) with ESMTPS id 8F219B21DBA for ; Mon, 18 Dec 2023 10:47:58 +0000 (UTC) Received: from localhost.localdomain (localhost.localdomain [127.0.0.1]) by smtp.subspace.kernel.org (Postfix) with ESMTP id C1A711947A; Mon, 18 Dec 2023 10:47:29 +0000 (UTC) X-Original-To: linux-kernel@vger.kernel.org Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 14ACE1945D; Mon, 18 Dec 2023 10:47:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 000531FB; Mon, 18 Dec 2023 02:48:10 -0800 (PST) Received: from [10.57.46.32] (unknown [10.57.46.32]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id D4F623F738; Mon, 18 Dec 2023 02:47:23 -0800 (PST) Message-ID: <1d57590d-2ecf-4bf6-9c8f-2a9d1ba08aaa@arm.com> Date: Mon, 18 Dec 2023 10:47:23 +0000 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 7/8] dt-bindings: arm: Add support for TPDM CMB MSR register Content-Language: en-GB To: Krzysztof Kozlowski , Tao Zhang , Mathieu Poirier , Alexander Shishkin , Konrad Dybcio , Mike Leach , Rob Herring , Krzysztof Kozlowski Cc: Jinlong Mao , Leo Yan , Greg Kroah-Hartman , coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Tingwei Zhang , Yuanfang Zhang , Trilok Soni , Song Chai , linux-arm-msm@vger.kernel.org, andersson@kernel.org References: <1700533494-19276-1-git-send-email-quic_taozha@quicinc.com> <1700533494-19276-8-git-send-email-quic_taozha@quicinc.com> From: Suzuki K Poulose In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Tao Zhang, On 21/11/2023 07:24, Krzysztof Kozlowski wrote: > On 21/11/2023 03:24, Tao Zhang wrote: >> Add property "qcom,cmb_msr_num" to support CMB MSR(mux select register) >> for TPDM. It specifies the number of CMB MSR registers supported by >> the TDPM. >> >> Signed-off-by: Tao Zhang >> Signed-off-by: Mao Jinlong >> --- > > I prefer not to take any new Qualcomm Coresight bindings or Qualcomm SoC > DTS nodes with Coresight till we fix all existing warnings. I don't know > how to fix them, so I need help with them. No such fixing happened so > far from Qcom, so pushback is my only way to get any attention. > > I already commented on this in other email thread. Are you addressing this ? Suzuki > > Best regards, > Krzysztof >