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Mon, 18 Dec 2023 04:09:00 -0800 (PST) Received: from localhost.localdomain ([117.207.27.21]) by smtp.gmail.com with ESMTPSA id j18-20020a170902c3d200b001d368c778dasm1285709plj.235.2023.12.18.04.08.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 Dec 2023 04:09:00 -0800 (PST) From: Manivannan Sadhasivam To: andersson@kernel.org, konrad.dybcio@linaro.org, vkoul@kernel.org, sboyd@kernel.org, mturquette@baylibre.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org Cc: linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, quic_cang@quicinc.com, Manivannan Sadhasivam Subject: [PATCH v2 16/16] arm64: dts: qcom: sm8550: Fix UFS PHY clocks Date: Mon, 18 Dec 2023 17:37:12 +0530 Message-Id: <20231218120712.16438-17-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20231218120712.16438-1-manivannan.sadhasivam@linaro.org> References: <20231218120712.16438-1-manivannan.sadhasivam@linaro.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit QMP PHY used in SM8550 requires 3 clocks: * ref - 19.2MHz reference clock from RPMh * ref_aux - Auxiliary reference clock from GCC * qref - QREF clock from TCSR Fixes: 35cf1aaab169 ("arm64: dts: qcom: sm8550: Add UFS host controller and phy nodes") Signed-off-by: Manivannan Sadhasivam --- arch/arm64/boot/dts/qcom/sm8550.dtsi | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi index baa8540868a4..386ffd0d72c4 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -1891,9 +1891,12 @@ crypto: crypto@1dfa000 { ufs_mem_phy: phy@1d80000 { compatible = "qcom,sm8550-qmp-ufs-phy"; reg = <0x0 0x01d80000 0x0 0x2000>; - clocks = <&tcsr TCSR_UFS_CLKREF_EN>, - <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; - clock-names = "ref", "ref_aux"; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, + <&tcsr TCSR_UFS_CLKREF_EN>; + clock-names = "ref", + "ref_aux", + "qref"; power-domains = <&gcc UFS_MEM_PHY_GDSC>; -- 2.25.1