Received: by 2002:a05:7412:8598:b0:f9:33c2:5753 with SMTP id n24csp513500rdh; Tue, 19 Dec 2023 06:00:46 -0800 (PST) X-Google-Smtp-Source: AGHT+IGp+Cm9YnX0C4vdAii5Bivkf6Y5JVbR6ANblWzlWFUZKb+5ecemSoj+yfQA+qVkWjy6a3z1 X-Received: by 2002:a2e:9b4d:0:b0:2cc:641d:d567 with SMTP id o13-20020a2e9b4d000000b002cc641dd567mr2207445ljj.37.1702994446492; Tue, 19 Dec 2023 06:00:46 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1702994446; cv=none; d=google.com; s=arc-20160816; b=Vmk/nWU53NgD7NIbbppJE9CPnEuXzVpsxjYjQoYK9l2rmPjPHdyvTf1sipCT9ml/AB vqn67bQNBL3nJRy8tZZje92pmgV6sJJD0qoA8ofXYVxAzQLKie5wyZe03eeiimjURi4Z fnKApwlDs1InnAj/xkgRJeO46eaF0+jw7Q6ZYtQwVQwptUCpdYHEOJ1dGlhXmMA27Onz qkglPna13g/+ydYfwd72B+nnSaJquyuhlWoIHY1FRE8c/ZFj4ONSXoWDyibQ6m1tsGV9 d01K6WcIu2mmO7zvt4ES4Wjp19c7co5QDGkLoh50ty2q+NP0M0Pn3H92EkJsk78Yc52L yXiw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=mime-version:list-unsubscribe:list-subscribe:list-id:precedence :message-id:date:subject:cc:to:from:dkim-signature; bh=vrQRABYwqM+SKciK6QnDbdhPJs3s9lNni1A1JyALLqo=; fh=mFC8nmckJLq19l2a2JACcOVBANdLlvDzOiUZ3OvRdps=; b=tpURbWptPoM+dCvmsk8wn2HKmsPskmKvGgKRs+/Q5kQ8Rn9tVnXnQjOlT0RC0asVAX gn/BvyX/1ReEOmkBjgeQENYlJs2c6bJaScsvKzF82bWyn0bD6ryMkMa6swdfgpoAw1B2 cFKDSOqlAKVXTTghAaO1GP/EyXX9NK7Vqrk7iJk0214VndZSoXlgZ1cgfPdhA/K/BnH7 FYn/J4kj5rQThJhrPC4Gtsfc6ZwXJ2ifzkCo9HnUpWOvl+OLeBu+NTRufnO7mTnVsUiv 75DzuLfe8VPzLUPUULnWs6JhnZCLWf3DlmZEPfGEXPZPOm6Ii2r37ht05CuL4uIHHo/n cXZQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=QgvM7Pal; spf=pass (google.com: domain of linux-kernel+bounces-5299-linux.lists.archive=gmail.com@vger.kernel.org designates 2604:1380:4601:e00::3 as permitted sender) smtp.mailfrom="linux-kernel+bounces-5299-linux.lists.archive=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Return-Path: Received: from am.mirrors.kernel.org (am.mirrors.kernel.org. [2604:1380:4601:e00::3]) by mx.google.com with ESMTPS id n10-20020a05640205ca00b0055122671ad8si8536579edx.165.2023.12.19.06.00.46 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Dec 2023 06:00:46 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel+bounces-5299-linux.lists.archive=gmail.com@vger.kernel.org designates 2604:1380:4601:e00::3 as permitted sender) client-ip=2604:1380:4601:e00::3; Authentication-Results: mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=QgvM7Pal; spf=pass (google.com: domain of linux-kernel+bounces-5299-linux.lists.archive=gmail.com@vger.kernel.org designates 2604:1380:4601:e00::3 as permitted sender) smtp.mailfrom="linux-kernel+bounces-5299-linux.lists.archive=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: from smtp.subspace.kernel.org (wormhole.subspace.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by am.mirrors.kernel.org (Postfix) with ESMTPS id 15F571F25682 for ; Tue, 19 Dec 2023 14:00:46 +0000 (UTC) Received: from localhost.localdomain (localhost.localdomain [127.0.0.1]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 9A1C91A702; Tue, 19 Dec 2023 14:00:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="QgvM7Pal" X-Original-To: linux-kernel@vger.kernel.org Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 851E11A587; Tue, 19 Dec 2023 14:00:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Received: from pps.filterd (m0279865.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.24/8.17.1.24) with ESMTP id 3BJDDHlw010251; Tue, 19 Dec 2023 14:00:09 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= from:to:cc:subject:date:message-id:mime-version:content-type; s= qcppdkim1; bh=vrQRABYwqM+SKciK6QnDbdhPJs3s9lNni1A1JyALLqo=; b=Qg vM7PalMGRybsvHu9EzdH3ER1yy7hQPZH19sbPtjGwZmbWj5JhvOFMh3UmpbS0hVn hJHn7vs8yhfrxSdp0XIxtUkAJD4hMmgUegpWFbS9ksh3VskqH4yiCn6KVuFfgY6D PN2s7kdeYfyC6+gaUphApGtwz9pVyl9MKr0pryb6ZOIIQTRBNqtygZ/ao6XZ9bwU g53H2OahZatRJuYAaK1MIVsfgA5yQ8j4H3NSx+BHXVlDrBYlSvCWR2MI96cuJX8T 0scrjmyIBzXiWiBjyXNF1DQ9JGHvVV8UB8hvJE7zIYMEL2lTpaUuQTspgLbKpYHr FqZam19G87rEv8wXl3ig== Received: from nalasppmta01.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3v360yh3qs-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 19 Dec 2023 14:00:08 +0000 (GMT) Received: from nalasex01c.na.qualcomm.com (nalasex01c.na.qualcomm.com [10.47.97.35]) by NALASPPMTA01.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 3BJE07qC002259 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 19 Dec 2023 14:00:08 GMT Received: from hu-bibekkum-hyd.qualcomm.com (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Tue, 19 Dec 2023 06:00:01 -0800 From: Bibek Kumar Patro To: , , , , , , , , , , , , , , CC: , , , , , Bibek Kumar Patro Subject: [PATCH v5 0/5] iommu/arm-smmu: introduction of ACTLR implementation for Qualcomm SoCs Date: Tue, 19 Dec 2023 19:29:42 +0530 Message-ID: <20231219135947.1623-1-quic_bibekkum@quicinc.com> X-Mailer: git-send-email 2.17.1 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: 7Vs_90ndUH0lhhlu9JtjFZPD4sTAhxlY X-Proofpoint-ORIG-GUID: 7Vs_90ndUH0lhhlu9JtjFZPD4sTAhxlY X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.997,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-12-09_01,2023-12-07_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 suspectscore=0 priorityscore=1501 spamscore=0 mlxlogscore=999 adultscore=0 bulkscore=0 clxscore=1015 mlxscore=0 malwarescore=0 phishscore=0 impostorscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2311290000 definitions=main-2312190104 This patch series consist of five parts and covers the following: 1. Re-enable context caching for Qualcomm SoCs to retain prefetcher settings during reset and runtime suspend. 2. Remove cfg inside qcom_smmu structure and replace it with single pointer to qcom_smmu_match_data avoiding replication of multiple members from same. 3. Introduce intital set of driver changes to implement ACTLR register for custom prefetcher settings in Qualcomm SoCs. 4. Add ACTLR data and implementation operations for SM8550. 5. Add ACTLR data and implementation operations for SC7280. Changes in v5 from v4: New addition: - Modify copyright year in arm-smmu-qcom.h to 2023 from 2022. Changes to incorporate suggestions from Dmitry as follows: - Modify the defines for prefetch in (foo << bar) format as suggested.(FIELD_PREP could not be used in defines is not inside any block/function) Changes to incorporate suggestions from Konrad as follows: - Shift context caching enablement patch as 1/5 instead of 5/5 to be picked up as independent patch. - Fix the codestyle to orient variables in reverse xmas tree format for patch 1/5. - Fix variable name in patch 1/5 as suggested. - evaluate for return check (Return check is not needed for arm_mmu500_reset, 0 being only return val). Link to v3: https://lore.kernel.org/all/20231215101827.30549-1-quic_bibekkum@quicinc.com/ Changes in v4 from v3: New addition: - Remove actlrcfg_size and use NULL end element instead to traverse the actlr table, as this would be a cleaner approach by removing redundancy of actlrcfg_size. - Renaming of actlr set function to arm_smmu_qcom based proprietary convention. - break from loop once sid is found and ACTLR value is initialized in qcom_smmu_set_actlr. - Modify the GFX prefetch value separating into 2 sensible defines. - Modify comments for prefetch defines as per SMMU-500 TRM. Changes to incorporate suggestions from Konrad as follows: - Use Reverse-Christmas-tree sorting wherever applicable. - Pass arguments directly to arm_smmu_set_actlr instead of creating duplicate variables. - Use array indexing instead of direct pointer addressed by new addition of eliminating actlrcfg_size. - Switch the HEX value's case from upper to lower case in SC7280 actlrcfg table. Changes to incorporate suggestions from Dmitry as follows: - Separate changes not related to ACTLR support to different commit with patch 5/5. - Using pointer to struct for arguments in smr_is_subset(). Changes to incorporate suggestions from Bjorn as follows: - fix the commit message for patch 2/5 to properly document the value space to avoid confusion. Fixed build issues reported by kernel test robot [1] for arm64-allyesconfig [2]. [1]: https://lore.kernel.org/all/202312011750.Pwca3TWE-lkp@intel.com/ [2]: https://download.01.org/0day-ci/archive/20231201/202312011750.Pwca3TWE-lkp@intel.com/config Link to v3: https://lore.kernel.org/all/20231127145412.3981-1-quic_bibekkum@quicinc.com/ Changes in v3 from v2: New addition: - Include patch 3/4 for adding ACTLR support and data for SC7280. - Add driver changes for actlr support in gpu smmu. - Add target wise actlr data and implementation ops for gpu smmu. Changes to incorporate suggestions from Robin as follows: - Match the ACTLR values with individual corresponding SID instead of assuming that any SMR will be programmed to match a superset of the data. - Instead of replicating each elements from qcom_smmu_match_data to qcom_smmu structre during smmu device creation, replace the replicated members with qcom_smmu_match_data structure inside qcom_smmu structre and handle the dereference in places that requires them. Changes to incorporate suggestions from Dmitry and Konrad as follows: - Maintain actlr table inside a single structure instead of nested structure. - Rename prefetch defines to more appropriately describe their behavior. - Remove SM8550 specific implementation ops and roll back to default qcom_smmu_500_impl implementation ops. - Add back the removed comments which are NAK. - Fix commit description for patch 4/4. Link to v2: https://lore.kernel.org/all/20231114135654.30475-1-quic_bibekkum@quicinc.com/ Changes in v2 from v1: - Incorporated suggestions on v1 from Dmitry,Konrad,Pratyush. - Added defines for ACTLR values. - Linked sm8550 implementation structure to corresponding compatible string. - Repackaged actlr value set implementation to separate function. - Fixed indentation errors. - Link to v1: https://lore.kernel.org/all/20231103215124.1095-1-quic_bibekkum@quicinc.com/ Changes in v1 from RFC: - Incorporated suggestion form Robin on RFC - Moved the actlr data table into driver, instead of maintaining it inside soc specific DT and piggybacking on exisiting iommus property (iommu = ) to set this value during smmu probe. - Link to RFC: https://lore.kernel.org/all/a01e7e60-6ead-4a9e-ba90-22a8a6bbd03f@quicinc.com/ Bibek Kumar Patro (5): iommu/arm-smmu: re-enable context caching in smmu reset operation iommu/arm-smmu: refactor qcom_smmu structure to include single pointer iommu/arm-smmu: introduction of ACTLR for custom prefetcher settings iommu/arm-smmu: add ACTLR data and support for SM8550 iommu/arm-smmu: add ACTLR data and support for SC7280 .../iommu/arm/arm-smmu/arm-smmu-qcom-debug.c | 2 +- drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 185 +++++++++++++++++- drivers/iommu/arm/arm-smmu/arm-smmu-qcom.h | 8 +- drivers/iommu/arm/arm-smmu/arm-smmu.c | 5 +- drivers/iommu/arm/arm-smmu/arm-smmu.h | 5 + 5 files changed, 195 insertions(+), 10 deletions(-) -- 2.17.1