Received: by 2002:a05:7412:d008:b0:f9:6acb:47ec with SMTP id bd8csp330144rdb; Tue, 19 Dec 2023 19:50:07 -0800 (PST) X-Google-Smtp-Source: AGHT+IHMi0Sh7HcvHuWZjnBmzPp4WUeoROfa8tpcdu1gTC28VeNOJsDyhtbDgqMibZn/LTbEA69J X-Received: by 2002:a05:620a:4404:b0:77f:61f0:5416 with SMTP id v4-20020a05620a440400b0077f61f05416mr24717036qkp.56.1703044206862; Tue, 19 Dec 2023 19:50:06 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1703044206; cv=none; d=google.com; s=arc-20160816; b=HBnHKOlpknlzn03kdcVfWOUjy+fxzGF3m73yNQyBIQBLOcAhVbTu2mNR7JpQA8ivpX y7sBppf3ur8d2Lq8M8NBCKQPvxIQ2H9DtS7PPqzcmvDMlTxZbGRmwj2Mp8cXD/4hhEwZ PbpkxcwMRDYBip4lHHrTdnMlIGOZ5l/53U+HRtROyQTYO/67Q/Drsptc4rvmNZ8zFqtS Mwj8uY8wD4flvhAYBp0V07z1pysw1KTk0EfLxNIlyd4OkPC0WmV1xkwL4B4m59k4njcK NFbQqEZmPnLl7ZjfMuLTlhoES7ap0CCeoKg2MoNoRPdEZ2FJQEMmYbosFVZ3TvZn7Go1 y6Ow== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=in-reply-to:content-transfer-encoding:content-disposition :mime-version:list-unsubscribe:list-subscribe:list-id:precedence :references:message-id:subject:cc:to:from:date:dkim-signature; bh=cV23V7TOvb67CyEBq2y7tG+sTh2KHoQeq84YdzqhXCE=; fh=v7FI1Kbx461+Qsj5j8r14ypGOvcKQh2Yba5Ofs8H2I0=; b=mN96ukGkaCPs9ivrAT1VlCZ6TKA6xao8jiE1oi8QGujApiWFcG+B5xLn1ERsrbMeSM HPyDcY8zOdBmfuaXn/0GUHC17PSbpEwhRX353lTu6wtj6f0gjbz6wpPILbtILIMMlmHx NY1090Tc+fkJsArKZGuUyJasKtM3uK1TW873qRYZOVqO4KllrJaSfFoVhmni5onHKfW0 KltfYLNCVinBL4bUXhjoTaqvNfWa//sSSI9vGYBjAXT0G+BZcr3f+83Eh778YPGvMF6d hv+f0bx7Mr28OJmENvRynZeXR8uYebUOPYJF1s7zAomJQrkyHunCExppGRWszsx5IqlX ztNw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ventanamicro.com header.s=google header.b=TRi5q9lD; spf=pass (google.com: domain of linux-kernel+bounces-6334-linux.lists.archive=gmail.com@vger.kernel.org designates 147.75.199.223 as permitted sender) smtp.mailfrom="linux-kernel+bounces-6334-linux.lists.archive=gmail.com@vger.kernel.org" Return-Path: Received: from ny.mirrors.kernel.org (ny.mirrors.kernel.org. [147.75.199.223]) by mx.google.com with ESMTPS id bj39-20020a05620a192700b0077f01c246aesi27869qkb.304.2023.12.19.19.50.06 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Dec 2023 19:50:06 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel+bounces-6334-linux.lists.archive=gmail.com@vger.kernel.org designates 147.75.199.223 as permitted sender) client-ip=147.75.199.223; Authentication-Results: mx.google.com; dkim=pass header.i=@ventanamicro.com header.s=google header.b=TRi5q9lD; spf=pass (google.com: domain of linux-kernel+bounces-6334-linux.lists.archive=gmail.com@vger.kernel.org designates 147.75.199.223 as permitted sender) smtp.mailfrom="linux-kernel+bounces-6334-linux.lists.archive=gmail.com@vger.kernel.org" Received: from smtp.subspace.kernel.org (wormhole.subspace.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ny.mirrors.kernel.org (Postfix) with ESMTPS id 8C9221C212E5 for ; Wed, 20 Dec 2023 03:50:06 +0000 (UTC) Received: from localhost.localdomain (localhost.localdomain [127.0.0.1]) by smtp.subspace.kernel.org (Postfix) with ESMTP id D1CB7BE76; Wed, 20 Dec 2023 03:49:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=ventanamicro.com header.i=@ventanamicro.com header.b="TRi5q9lD" X-Original-To: linux-kernel@vger.kernel.org Received: from mail-io1-f42.google.com (mail-io1-f42.google.com [209.85.166.42]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E197C156E2 for ; Wed, 20 Dec 2023 03:49:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=ventanamicro.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ventanamicro.com Received: by mail-io1-f42.google.com with SMTP id ca18e2360f4ac-7b7fb34265fso38575639f.3 for ; Tue, 19 Dec 2023 19:49:44 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1703044184; x=1703648984; darn=vger.kernel.org; h=in-reply-to:content-transfer-encoding:content-disposition :mime-version:references:message-id:subject:cc:to:from:date:from:to :cc:subject:date:message-id:reply-to; bh=cV23V7TOvb67CyEBq2y7tG+sTh2KHoQeq84YdzqhXCE=; b=TRi5q9lDJZdfAvtKFYNNTleePu2PoxvqaQK4mpAkJLU9znxosjXHvMmfMxx3Ejlmca pvB+tPF+c8YyQ71i0Et++snbh3hCO1Kft8jbif26EcWgiKgamHvIi0o0G1UGeA2NJIef u66nUB+G4Mc7Y+W57xBfd54rBOckBAY+dQ+xv3byLrMryRpPWLT8PIrPKEQhzB0/SkAV 3h5eSbwgJNSH+AC6z94xMsOyjoUrwL33GpsABs/x3Xk8mGN2OnD9BhWjwsLxPfSrpRGw ybnYSNg9T5bRELx4pK9CWWNJalLxSNF+t1jMI2ZIuY6Yog08AaNk8iKruj5WMY0QfPg1 7EIg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1703044184; x=1703648984; h=in-reply-to:content-transfer-encoding:content-disposition :mime-version:references:message-id:subject:cc:to:from:date :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=cV23V7TOvb67CyEBq2y7tG+sTh2KHoQeq84YdzqhXCE=; b=JH9nC1TSk+NSUQHFGfBbeIEB6l8BpqgGUTClr18ROCYSRo+SFlm3vbKiCSS16+tdQ4 7t0oPwYv+jhUSUzM62vYlenW97/JBowo7Rue8ZhgwRzSynylFpwm8/bUXz3077aMQPag sFIar+VZ7yntbRe1d+GffwJPML/9N2dzpadPF8tMGF03LumWZ3u8ccXWcFJ8aXbj6gf8 FB+t0CghXf1gAU6xhBXXFt3XTYp/ussRITCGBPklhQLFDMbyc1dYgMZqXLqqBnzPLiBW aJY63G0wTIoRrCSSd8vyspyabXBlQo6KEk6tE6clqzGFxsNkqyFiz3TvGKp1ymypumJC LUjA== X-Gm-Message-State: AOJu0YzfI2/OqsoOMBhOuJDT4/Sr6rNeyuVkxscm7SpqxjO2kT5ZxD5z H9/bCsxKEDSxF12jg+lIN2eepPmGQRcpeYtCCqM= X-Received: by 2002:a6b:7f0c:0:b0:7b7:faa5:954f with SMTP id l12-20020a6b7f0c000000b007b7faa5954fmr1627037ioq.23.1703044183845; Tue, 19 Dec 2023 19:49:43 -0800 (PST) Received: from sunil-laptop ([106.51.83.242]) by smtp.gmail.com with ESMTPSA id r9-20020a6bd909000000b007b42bf452f4sm6509305ioc.33.2023.12.19.19.49.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Dec 2023 19:49:43 -0800 (PST) Date: Wed, 20 Dec 2023 09:19:32 +0530 From: Sunil V L To: "Rafael J. Wysocki" Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, linux-acpi@vger.kernel.org, linux-pci@vger.kernel.org, Catalin Marinas , Will Deacon , Paul Walmsley , Palmer Dabbelt , Albert Ou , Len Brown , Anup Patel , Thomas Gleixner , Bjorn Helgaas , Haibo Xu , Conor Dooley , Andrew Jones , =?utf-8?B?QmrDtnJuIFTDtnBlbA==?= , Marc Zyngier Subject: Re: [RFC PATCH v3 00/17] RISC-V: ACPI: Add external interrupt controller support Message-ID: References: <20231219174526.2235150-1-sunilvl@ventanamicro.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: On Tue, Dec 19, 2023 at 06:50:19PM +0100, Rafael J. Wysocki wrote: > On Tue, Dec 19, 2023 at 6:45 PM Sunil V L wrote: > > > > This series adds support for the below ECR approved by ASWG. > > 1) MADT - https://drive.google.com/file/d/1oMGPyOD58JaPgMl1pKasT-VKsIKia7zR/view?usp=sharing > > > > The series primarily enables irqchip drivers for RISC-V ACPI based > > platforms. > > > > The series can be broadly categorized like below. > > > > 1) PCI ACPI related functions are migrated from arm64 to common file so > > that we don't need to duplicate them for RISC-V. > > > > 2) Introduced support for fw_devlink for ACPI nodes for IRQ dependency. > > This helps to support deferred probe of interrupt controller drivers. > > > > 3) Modified pnp_irq() to try registering the IRQ again if it sees it in > > disabled state. This solution is similar to how > > platform_get_irq_optional() works for regular platform devices. > > > > 4) Added support for re-ordering the probe of interrupt controllers when > > IRQCHIP_ACPI_DECLARE is used. > > > > 5) ACPI support added in RISC-V interrupt controller drivers. > > > > This series is based on Anup's AIA v11 series. Since Anup's AIA v11 is > > not merged yet and first time introducing fw_devlink, deferred probe and > > reordering support for IRQCHIP probe, this series is still kept as RFC. > > Looking forward for the feedback! > > > > Changes since RFC v2: > > 1) Introduced fw_devlink for ACPI nodes for IRQ dependency. > > 2) Dropped patches in drivers which are not required due to > > fw_devlink support. > > 3) Dropped pci_set_msi() patch and added a patch in > > pci_create_root_bus(). > > 4) Updated pnp_irq() patch so that none of the actual PNP > > drivers need to change. > > > > Changes since RFC v1: > > 1) Abandoned swnode approach as per Marc's feedback. > > 2) To cope up with AIA series changes which changed irqchip driver > > probe from core_initcall() to platform_driver, added patches > > to support deferred probing. > > 3) Rebased on top of Anup's AIA v11 and added tags. > > > > To test the series, > > > > 1) Qemu should be built using the riscv_acpi_b2_v8 branch at > > https://github.com/vlsunil/qemu.git > > > > 2) EDK2 should be built using the instructions at: > > https://github.com/tianocore/edk2/blob/master/OvmfPkg/RiscVVirt/README.md > > > > 3) Build Linux using this series on top of Anup's AIA v11 series. > > > > Run Qemu: > > qemu-system-riscv64 \ > > -M virt,pflash0=pflash0,pflash1=pflash1,aia=aplic-imsic \ > > -m 2G -smp 8 \ > > -serial mon:stdio \ > > -device virtio-gpu-pci -full-screen \ > > -device qemu-xhci \ > > -device usb-kbd \ > > -blockdev node-name=pflash0,driver=file,read-only=on,filename=RISCV_VIRT_CODE.fd \ > > -blockdev node-name=pflash1,driver=file,filename=RISCV_VIRT_VARS.fd \ > > -netdev user,id=net0 -device virtio-net-pci,netdev=net0 \ > > -kernel arch/riscv/boot/Image \ > > -initrd rootfs.cpio \ > > -append "root=/dev/ram ro console=ttyS0 rootwait earlycon=uart8250,mmio,0x10000000" > > > > To boot with APLIC only, use aia=aplic. > > To boot with PLIC, remove aia= option. > > > > This series is also available in acpi_b2_v3_riscv_aia_v11 branch at > > https://github.com/vlsunil/linux.git > > > > Based-on: 20231023172800.315343-1-apatel@ventanamicro.com > > (https://lore.kernel.org/lkml/20231023172800.315343-1-apatel@ventanamicro.com/) > > > > Sunil V L (17): > > arm64: PCI: Migrate ACPI related functions to pci-acpi.c > > RISC-V: ACPI: Implement PCI related functionality > > PCI: Make pci_create_root_bus() declare its reliance on MSI domains > > ACPI: Add fw_devlink support for ACPI fwnode for IRQ dependency > > ACPI: irq: Add support for deferred probe in acpi_register_gsi() > > pnp.h: Reconfigure IRQ in pnp_irq() to support deferred probe > > ACPI: scan.c: Add weak arch specific function to reorder the IRQCHIP > > probe > > ACPI: RISC-V: Implement arch function to reorder irqchip probe entries > > irqchip: riscv-intc: Add ACPI support for AIA > > irqchip: riscv-imsic: Add ACPI support > > irqchip: riscv-aplic: Add ACPI support > > irqchip: irq-sifive-plic: Add ACPI support > > ACPI: bus: Add RINTC IRQ model for RISC-V > > ACPI: bus: Add acpi_riscv_init function > > ACPI: RISC-V: Create APLIC platform device > > ACPI: RISC-V: Create PLIC platform device > > irqchip: riscv-intc: Set ACPI irqmodel > > JFYI, I have no capacity to provide any feedback on this till 6.8-rc1 is out. > No worries!. I will wait for your feedback. Thanks! Sunil