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Message-ID: <ccd67437-39cb-4fea-98aa-4dfae5f4c1d0@quicinc.com>
Date: Wed, 20 Dec 2023 13:38:23 +0530
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Subject: Re: [PATCH v5 1/5] iommu/arm-smmu: re-enable context caching in smmu
 reset operation
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To: Konrad Dybcio <konrad.dybcio@linaro.org>, <will@kernel.org>,
        <robin.murphy@arm.com>, <joro@8bytes.org>,
        <dmitry.baryshkov@linaro.org>, <jsnitsel@redhat.com>,
        <quic_bjorande@quicinc.com>, <mani@kernel.org>,
        <quic_eberman@quicinc.com>, <robdclark@chromium.org>,
        <u.kleine-koenig@pengutronix.de>, <robh@kernel.org>,
        <vladimir.oltean@nxp.com>, <quic_pkondeti@quicinc.com>,
        <quic_molvera@quicinc.com>
CC: <linux-arm-msm@vger.kernel.org>, <linux-arm-kernel@lists.infradead.org>,
        <iommu@lists.linux.dev>, <linux-kernel@vger.kernel.org>,
        <qipl.kernel.upstream@quicinc.com>
References: <20231219135947.1623-1-quic_bibekkum@quicinc.com>
 <20231219135947.1623-2-quic_bibekkum@quicinc.com>
 <810ee42b-49c9-4184-b5aa-a95261faf77a@linaro.org>
From: Bibek Kumar Patro <quic_bibekkum@quicinc.com>
In-Reply-To: <810ee42b-49c9-4184-b5aa-a95261faf77a@linaro.org>
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On 12/19/2023 11:29 PM, Konrad Dybcio wrote:
> On 19.12.2023 14:59, Bibek Kumar Patro wrote:
>> Default MMU-500 reset operation disables context caching in
>> prefetch buffer. It is however expected for context banks using
>> the ACTLR register to retain their prefetch value during reset
>> and runtime suspend.
>>
>> Replace default MMU-500 reset operation with Qualcomm specific reset
>> operation which envelope the default reset operation and re-enables
>> context caching in prefetch buffer for Qualcomm SoCs.
>>
>> Suggested-by: Konrad Dybcio <konrad.dybcio@linaro.org>
> Suggested-by implies I came up with this being a solution to
> an issue.. definitely not the case!
> 

Noted, will send v6 by removing the Suggested by tag
and will address the return check as well.

Thanks,
Bibek

> Konrad