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Wed, 20 Dec 2023 08:23:32 GMT Received: from [10.216.36.155] (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Wed, 20 Dec 2023 00:23:28 -0800 Message-ID: Date: Wed, 20 Dec 2023 13:53:25 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:102.0) Gecko/20100101 Thunderbird/102.13.0 Subject: Re: [PATCH v2 29/34] media: iris: implement power management Content-Language: en-US To: Konrad Dybcio , , , , , , , , CC: , References: <1702899149-21321-1-git-send-email-quic_dikshita@quicinc.com> <1702899149-21321-30-git-send-email-quic_dikshita@quicinc.com> <20690d50-5f76-4371-97e6-dcee717ba935@linaro.org> From: Dikshita Agarwal In-Reply-To: <20690d50-5f76-4371-97e6-dcee717ba935@linaro.org> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 7bit X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: JsTIpkYLsC429TD24AKUDx-cPwefFv2p X-Proofpoint-GUID: JsTIpkYLsC429TD24AKUDx-cPwefFv2p X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.997,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-12-09_01,2023-12-07_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 spamscore=0 mlxscore=0 malwarescore=0 mlxlogscore=796 clxscore=1015 priorityscore=1501 adultscore=0 suspectscore=0 lowpriorityscore=0 bulkscore=0 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2311290000 definitions=main-2312200057 On 12/19/2023 5:54 PM, Konrad Dybcio wrote: > On 18.12.2023 12:32, Dikshita Agarwal wrote: >> From: Vikash Garodia >> >> Hardware specific power sequence include programming specific >> sequence of registers. Implements this sequence for iris3. >> >> Introduce video device suspend and resume using runtime PM. >> >> Also, implement iris3 specific calculation for clock and >> bus bandwidth which depends on hardware configuration, >> codec format, resolution and frame rate. >> >> Signed-off-by: Vikash Garodia >> Signed-off-by: Dikshita Agarwal >> --- > [...] > >> @@ -97,6 +103,7 @@ static int iris_probe(struct platform_device *pdev) > return dev_err_probe, drop __func__ Sure > > [...] > >> + ret = readl_relaxed_poll_timeout(base_addr + reg, val, ((val & mask) == exp_val), >> + sleep_us, timeout_us); >> + /* >> + * Memory barrier to make sure value is read correctly from the >> + * register. >> + */ >> + rmb(); > just drop _relaxed and return directly > Will check and do the needful. >> + >> + return ret; >> +} > [...] > >> + ret = read_register_with_poll_timeout(core, AON_WRAPPER_MVP_NOC_RESET_ACK, >> + 0x3, 0x3, 200, 2000); > that looks like a lot of bits/bitfields that deserve #defining in this > and some other functions > Will check this. > Konrad