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Wed, 20 Dec 2023 13:40:35 GMT Received: from [10.239.133.49] (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Wed, 20 Dec 2023 05:40:31 -0800 Message-ID: <98407ed5-5e0c-4bee-be4c-70b3d8972823@quicinc.com> Date: Wed, 20 Dec 2023 21:40:29 +0800 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH] arm64: dts: qcom: Add coresight nodes for sm8450 Content-Language: en-US To: Krzysztof Kozlowski , Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , "Krzysztof Kozlowski" , Conor Dooley CC: , , , Tingwei Zhang , Yuanfang Zhang , Tao Zhang , References: <20231220124009.16816-1-quic_jinlmao@quicinc.com> <439916dc-8f71-4998-b145-1d183d9e68f5@quicinc.com> <77ba0140-5b74-40d7-a923-4b270d661d3a@linaro.org> From: Jinlong Mao In-Reply-To: <77ba0140-5b74-40d7-a923-4b270d661d3a@linaro.org> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: ULhEewe5uUSLkhhTvWJRb1dyW4xG-V0H X-Proofpoint-GUID: ULhEewe5uUSLkhhTvWJRb1dyW4xG-V0H X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.997,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-12-09_01,2023-12-07_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 phishscore=0 priorityscore=1501 impostorscore=0 mlxscore=0 adultscore=0 spamscore=0 mlxlogscore=713 bulkscore=0 clxscore=1015 malwarescore=0 suspectscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2311290000 definitions=main-2312200097 On 12/20/2023 9:21 PM, Krzysztof Kozlowski wrote: > On 20/12/2023 14:07, Jinlong Mao wrote: >> >> >> On 12/20/2023 8:46 PM, Krzysztof Kozlowski wrote: >>> On 20/12/2023 13:40, Mao Jinlong wrote: >>>> Add coresight components on Qualcomm SM8450 Soc. The components include >>>> TMC ETF/ETR, ETE, STM, TPDM, CTI. >>>> >>>> Signed-off-by: Mao Jinlong >>>> --- >>>> arch/arm64/boot/dts/qcom/sm8450.dtsi | 742 +++++++++++++++++++++++++++ >>>> 1 file changed, 742 insertions(+) >>>> >>>> diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi >>>> index 1783fa78bdbc..112b5a069c94 100644 >>>> --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi >>>> +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi >>>> @@ -285,6 +285,192 @@ CLUSTER_SLEEP_1: cluster-sleep-1 { >>>> }; >>>> }; >>>> >>>> + ete0 { >>> >>> ete-0 >> Thanks for the review. >> >> In arm,embedded-trace-extension.yaml, the node name pattern is >> "^ete([0-9a-f]+)$". > > I don't understand why this binding requires ete name. It's not like it > is a generic name worth preserving. Also, the recommended suffix for > names is with '-'. > The number in the ete name should be the same as the number of the CPU. So we can know which CPU this ete belongs to from the name. I will update the binding in arm,embedded-trace-extension.yaml. Thanks Jinlong Mao > > Best regards, > Krzysztof >