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Message-ID: <cbbcb801-916a-445d-8b36-60d470b61d46@collabora.com>
Date: Wed, 20 Dec 2023 15:02:33 +0100
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Subject: Re: [PATCH v3 0/3] MediaTek clocks: Support mux indices list and 8195
 DP
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To: sboyd@kernel.org
Cc: mturquette@baylibre.com, matthias.bgg@gmail.com, wenst@chromium.org,
 msp@baylibre.com, amergnat@baylibre.com, yangyingliang@huawei.com,
 u.kleine-koenig@pengutronix.de, linux-clk@vger.kernel.org,
 linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
 linux-mediatek@lists.infradead.org, kernel@collabora.com
References: <20231103102533.69280-1-angelogioacchino.delregno@collabora.com>
From: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
In-Reply-To: <20231103102533.69280-1-angelogioacchino.delregno@collabora.com>
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Il 03/11/23 11:25, AngeloGioacchino Del Regno ha scritto:
> Changes in v3:
>   - Rebased on next-20231025
>   - Added comment in the code explaining why the dp/edp parents lists
>     are split in one PLL per interface
>   - Added a commit performing the same reparenting on MT8188 as well
> 
> Changes in v2:
>   - Rebased on next-20231018
> 

Hello Stephen,

friendly ping for this fully reviewed/tested series :-)

Cheers,
Angelo

> This series adds support to specify custom parent indices for MediaTek
> MUX clocks, necessary to avoid setting the same parent PLL for MT8195's
> top_dp and top_edp clocks, solving DP+eDP concurrent output issues.
> 
> No fixes tags are provided as the clk-mux commit introduces new logic
> and the actual MT8195 fix depends on that.
> 
> This commit was tested on the Acer Tomato Chromebook (MT8195) with
> dual concurrent display outputs (internal eDP panel and TypeC->DP->HDMI
> adapter connected to Samsung UE40JU6400 4k TV); resolution switch on
> DP was also tested; eDP output is not paused and internal display keeps
> working as expected.
> 
> 
> After feedback on v1 of this series (effectively the same as v2, except
> for the rebase), I looked for an alternative solution with using
> clk_set_rate_exclusive() as proposed. Couldn't find any, as that still
> doesn't give any guarantee about selecting the same PLL that the driver
> was manipulating before setting the right divider MUX, hence that still
> wouldn't work correctly.
> 
> For more context, please look at the conversation at [1].
> 
> Cheers!
> 
> [1] https://lore.kernel.org/linux-arm-kernel/20230713072138.84117-1-angelogioacchino.delregno@collabora.com
> 
> AngeloGioacchino Del Regno (3):
>    clk: mediatek: clk-mux: Support custom parent indices for muxes
>    clk: mediatek: mt8195-topckgen: Refactor parents for top_dp/edp muxes
>    clk: mediatek: mt8188-topckgen: Refactor parents for top_dp/edp muxes
> 
>   drivers/clk/mediatek/clk-mt8188-topckgen.c | 27 +++++++-------
>   drivers/clk/mediatek/clk-mt8195-topckgen.c | 27 ++++++++++----
>   drivers/clk/mediatek/clk-mux.c             | 14 +++++++
>   drivers/clk/mediatek/clk-mux.h             | 43 ++++++++++++++++++++--
>   4 files changed, 86 insertions(+), 25 deletions(-)
>