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Message-ID: <73dc7954-f005-4806-b7c0-a4d8a267de7b@collabora.com>
Date: Wed, 20 Dec 2023 16:46:28 +0200
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Subject: Re: [PATCH v5 3/4] riscv: dts: starfive: visionfive-v1: Setup
 ethernet phy
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To: Emil Renner Berthing <emil.renner.berthing@canonical.com>,
 Emil Renner Berthing <kernel@esmil.dk>, Conor Dooley <conor@kernel.org>,
 Rob Herring <robh+dt@kernel.org>,
 Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
 Paul Walmsley <paul.walmsley@sifive.com>, Palmer Dabbelt
 <palmer@dabbelt.com>, Albert Ou <aou@eecs.berkeley.edu>,
 Richard Cochran <richardcochran@gmail.com>, Andrew Lunn <andrew@lunn.ch>,
 Jacob Keller <jacob.e.keller@intel.com>
Cc: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org,
 linux-kernel@vger.kernel.org, netdev@vger.kernel.org, kernel@collabora.com
References: <20231220004638.2463643-1-cristian.ciocaltea@collabora.com>
 <20231220004638.2463643-4-cristian.ciocaltea@collabora.com>
 <CAJM55Z-CWHs1XMOYLOYQmB8qjZ=a3fhyGv3hJAN7bbbDQdEy0g@mail.gmail.com>
From: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
In-Reply-To: <CAJM55Z-CWHs1XMOYLOYQmB8qjZ=a3fhyGv3hJAN7bbbDQdEy0g@mail.gmail.com>
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On 12/20/23 15:48, Emil Renner Berthing wrote:
> Cristian Ciocaltea wrote:
>> The StarFive VisionFive V1 SBC uses a Motorcomm YT8521 PHY supporting
>> RGMII-ID, but requires manual adjustment of the RX internal delay to
>> work properly.
>>
>> The default RX delay provided by the driver is 1.95 ns, which proves to
>> be too high. Applying a 50% reduction seems to mitigate the issue.
>>
>> Also note this adjustment is not necessary on BeagleV Starlight SBC,
>> which uses a Microchip PHY.  Hence, there is no indication of a
>> misbehaviour on the GMAC side, but most likely the issue stems from
>> the Motorcomm PHY.
>>
>> While at it, drop the redundant gpio include, which is already provided
>> by jh7100-common.dtsi.
>>
>> Co-developed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
>> Signed-off-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
>> Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
>> Reviewed-by: Jacob Keller <jacob.e.keller@intel.com>
>> Reviewed-by: Andrew Lunn <andrew@lunn.ch>
>> ---
>>  .../jh7100-starfive-visionfive-v1.dts         | 22 ++++++++++++++++++-
>>  1 file changed, 21 insertions(+), 1 deletion(-)
>>
>> diff --git a/arch/riscv/boot/dts/starfive/jh7100-starfive-visionfive-v1.dts b/arch/riscv/boot/dts/starfive/jh7100-starfive-visionfive-v1.dts
>> index e82af72f1aaf..4e396f820660 100644
>> --- a/arch/riscv/boot/dts/starfive/jh7100-starfive-visionfive-v1.dts
>> +++ b/arch/riscv/boot/dts/starfive/jh7100-starfive-visionfive-v1.dts
>> @@ -6,7 +6,6 @@
>>
>>  /dts-v1/;
>>  #include "jh7100-common.dtsi"
>> -#include <dt-bindings/gpio/gpio.h>
>>
>>  / {
>>  	model = "StarFive VisionFive V1";
>> @@ -18,3 +17,24 @@ gpio-restart {
>>  		priority = <224>;
>>  	};
>>  };
>> +
>> +/*
>> + * The board uses a Motorcomm YT8521 PHY supporting RGMII-ID, but requires
>> + * manual adjustment of the RX internal delay to work properly.  The default
>> + * RX delay provided by the driver (1.95ns) is too high, but applying a 50%
>> + * reduction seems to mitigate the issue.
>> + *
>> + * It is worth noting the adjustment is not necessary on BeagleV Starlight SBC,
>> + * which uses a Microchip PHY.  Hence, most likely the Motorcomm PHY is the one
>> + * responsible for the misbehaviour, not the GMAC.
>> + */
>> +&mdio {
>> +	phy: ethernet-phy@0 {
>> +		reg = <0>;
>> +		rx-internal-delay-ps = <900>;
>> +	};
>> +};
>> +
>> +&gmac {
>> +	phy-handle = <&phy>;
>> +};
> 
> Alphabetical ordering here, please.

Yeah, I wasn't sure if the ordering is more important than having the
referenced nodes added before.  I suppose there's a need for v6. :-)

> /Emil