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From: Thomas Gleixner <tglx@linutronix.de>
To: =?utf-8?B?SmFtZXMgVGFpIFvmiLTlv5fls7Bd?= <james.tai@realtek.com>, Marc
 Zyngier
 <maz@kernel.org>, Rob
 Herring <robh+dt@kernel.org>, Krzysztof Kozlowski
 <krzysztof.kozlowski+dt@linaro.org>, Conor Dooley <conor+dt@kernel.org>
Cc: "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
 "devicetree@vger.kernel.org" <devicetree@vger.kernel.org>, kernel test
 robot <lkp@intel.com>, Dan Carpenter <error27@gmail.com>
Subject: RE: [PATCH v3 2/6] irqchip: Add interrupt controller support for
 Realtek DHC SoCs
In-Reply-To: <d9556a14e8d64f83b89a2d1d231003f4@realtek.com>
References: <20231129054339.3054202-1-james.tai@realtek.com>
 <20231129054339.3054202-3-james.tai@realtek.com> <87cyvgsocp.ffs@tglx>
 <d9556a14e8d64f83b89a2d1d231003f4@realtek.com>
Date: Wed, 20 Dec 2023 16:30:48 +0100
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On Tue, Dec 19 2023 at 03:15, James Tai [=E6=88=B4=E5=BF=97=E5=B3=B0] wrote:
>>On Wed, Nov 29 2023 at 13:43, James Tai wrote:
>>> +static inline void realtek_intc_clear_ints_bit(struct
>>> +realtek_intc_data *data, int bit) {
>>> +     writel(BIT(bit) & ~1, data->base + data->info->isr_offset);
>>
>>That '& ~1' solves what aside of preventing bit 0 from being written?
>>
> The ISR register uses bit 0 to clear or set ISR status.
> Write 0 to clear bits and write 1 to set bits.
> Therefore, to clear the interrupt status, bit 0 should consistently be
> set to '0'.

And how does BIT(bit) with 1 <=3D bit <=3D 31 end up having bit 0 set?

Also a comment explaining the reasoning here would be helpful.