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([2620:0:1000:8411:872c:d7b7:41e9:3edd]) by smtp.gmail.com with ESMTPSA id l17-20020a170902eb1100b001bf11cf2e21sm1995752plb.210.2023.12.21.11.29.25 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 21 Dec 2023 11:29:26 -0800 (PST) Message-ID: Date: Thu, 21 Dec 2023 11:29:25 -0800 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH RFC v3 09/11] scsi: ufs: core: Perform read back after disabling UIC_COMMAND_COMPL Content-Language: en-US To: Andrew Halaney , Andy Gross , Bjorn Andersson , Konrad Dybcio , Manivannan Sadhasivam , "James E.J. Bottomley" , "Martin K. Petersen" , Hannes Reinecke , Janek Kotas , Alim Akhtar , Avri Altman , Can Guo Cc: Will Deacon , linux-arm-msm@vger.kernel.org, linux-scsi@vger.kernel.org, linux-kernel@vger.kernel.org References: <20231221-ufs-reset-ensure-effect-before-delay-v3-0-2195a1b66d2e@redhat.com> <20231221-ufs-reset-ensure-effect-before-delay-v3-9-2195a1b66d2e@redhat.com> From: Bart Van Assche In-Reply-To: <20231221-ufs-reset-ensure-effect-before-delay-v3-9-2195a1b66d2e@redhat.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 12/21/23 11:09, Andrew Halaney wrote: > Currently, the UIC_COMMAND_COMPL interrupt is disabled and a wmb() is > used to complete the register write before any following writes. > > wmb() ensures the writes complete in that order, but completion doesn't > mean that it isn't stored in a buffer somewhere. The recommendation for > ensuring this bit has taken effect on the device is to perform a read > back to force it to make it all the way to the device. This is > documented in device-io.rst and a talk by Will Deacon on this can > be seen over here: > > https://youtu.be/i6DayghhA8Q?si=MiyxB5cKJXSaoc01&t=1678 > > Let's do that to ensure the bit hits the device. Because the wmb()'s > purpose wasn't to add extra ordering (on top of the ordering guaranteed > by writel()/readl()), it can safely be removed. > > Fixes: d75f7fe495cf ("scsi: ufs: reduce the interrupts for power mode change requests") > Signed-off-by: Andrew Halaney > --- > drivers/ufs/core/ufshcd.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/ufs/core/ufshcd.c b/drivers/ufs/core/ufshcd.c > index bb603769b029..75a03ee9a1ba 100644 > --- a/drivers/ufs/core/ufshcd.c > +++ b/drivers/ufs/core/ufshcd.c > @@ -4240,7 +4240,7 @@ static int ufshcd_uic_pwr_ctrl(struct ufs_hba *hba, struct uic_command *cmd) > * Make sure UIC command completion interrupt is disabled before > * issuing UIC command. > */ > - wmb(); > + ufshcd_readl(hba, REG_INTERRUPT_ENABLE); > reenable_intr = true; > } > spin_unlock_irqrestore(hba->host->host_lock, flags); Reviewed-by: Bart Van Assche