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Thu, 21 Dec 2023 21:09:29 -0800 (PST) X-Received: by 2002:a05:6870:3308:b0:203:6d48:cf9f with SMTP id x8-20020a056870330800b002036d48cf9fmr837917oae.79.1703221769679; Thu, 21 Dec 2023 21:09:29 -0800 (PST) Received: from localhost.localdomain ([2804:1b3:a802:7496:88a7:1b1a:a837:bebf]) by smtp.gmail.com with ESMTPSA id e15-20020aa7824f000000b006d9879ba6besm374346pfn.170.2023.12.21.21.09.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Dec 2023 21:09:29 -0800 (PST) From: Leonardo Bras To: guoren@kernel.org Cc: Leonardo Bras , linux-kernel@vger.kernel.org, paul.walmsley@sifive.com, palmer@dabbelt.com, alexghiti@rivosinc.com, charlie@rivosinc.com, xiao.w.wang@intel.com, david@redhat.com, panqinglin2020@iscas.ac.cn, rick.p.edgecombe@intel.com, willy@infradead.org, bjorn@rivosinc.com, conor.dooley@microchip.com, cleger@rivosinc.com, linux-riscv@lists.infradead.org, Guo Ren Subject: Re: [PATCH V2 4/4] riscv: mm: Optimize TASK_SIZE definition Date: Fri, 22 Dec 2023 02:09:05 -0300 Message-ID: X-Mailer: git-send-email 2.43.0 In-Reply-To: <20231221154702.2267684-5-guoren@kernel.org> References: <20231221154702.2267684-1-guoren@kernel.org> <20231221154702.2267684-5-guoren@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit On Thu, Dec 21, 2023 at 10:47:01AM -0500, guoren@kernel.org wrote: > From: Guo Ren > > Unify the TASK_SIZE definition with VA_BITS for better readability. > Add COMPAT mode user address space info in the comment. > > Signed-off-by: Guo Ren > Signed-off-by: Guo Ren > --- > arch/riscv/include/asm/pgtable.h | 7 ++++--- > 1 file changed, 4 insertions(+), 3 deletions(-) > > diff --git a/arch/riscv/include/asm/pgtable.h b/arch/riscv/include/asm/pgtable.h > index e415582276ec..d165ddae3b42 100644 > --- a/arch/riscv/include/asm/pgtable.h > +++ b/arch/riscv/include/asm/pgtable.h > @@ -866,6 +866,7 @@ static inline pte_t pte_swp_clear_exclusive(pte_t pte) > * Note that PGDIR_SIZE must evenly divide TASK_SIZE. > * Task size is: > * - 0x9fc00000 (~2.5GB) for RV32. > + * - 0x80000000 ( 2GB) for RV64 compat mode > * - 0x4000000000 ( 256GB) for RV64 using SV39 mmu > * - 0x800000000000 ( 128TB) for RV64 using SV48 mmu > * - 0x100000000000000 ( 64PB) for RV64 using SV57 mmu > @@ -877,11 +878,11 @@ static inline pte_t pte_swp_clear_exclusive(pte_t pte) > * Similarly for SV57, bits 63–57 must be equal to bit 56. > */ > #ifdef CONFIG_64BIT > -#define TASK_SIZE_64 (PGDIR_SIZE * PTRS_PER_PGD / 2) > +#define TASK_SIZE_64 (UL(1) << (VA_BITS - 1)) Checked for l5, l4 and l3, and it seems a correct replacement. > > #ifdef CONFIG_COMPAT > -#define TASK_SIZE_32 (_AC(0x80000000, UL)) > -#define TASK_SIZE (test_thread_flag(TIF_32BIT) ? \ > +#define TASK_SIZE_32 (UL(1) << (VA_BITS_SV32 - 1)) Oh, much better. Thanks for removing the magic number :) > +#define TASK_SIZE (is_compat_task() ? \ > TASK_SIZE_32 : TASK_SIZE_64) > #else > #define TASK_SIZE TASK_SIZE_64 > -- > 2.40.1 > That's much more readable IMO now. Thanks! FWIW: Reviewed-by: Leonardo Bras