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Message-ID: <d3a80bd0-6316-42af-a09a-172a026f19a6@flygoat.com>
Date: Fri, 22 Dec 2023 12:40:39 +0000
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Subject: Re: [PATCH v2 05/10] MIPS: Refactor mips_cps_core_entry
 implementation
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To: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Cc: linux-mips@vger.kernel.org, linux-kernel@vger.kernel.org,
 gregory.clement@bootlin.com, vladimir.kondratiev@intel.com
References: <20231027221106.405666-1-jiaxun.yang@flygoat.com>
 <20231027221106.405666-6-jiaxun.yang@flygoat.com>
 <ZYV+jQ5M/Hu2aTgq@alpha.franken.de>
From: Jiaxun Yang <jiaxun.yang@flygoat.com>
In-Reply-To: <ZYV+jQ5M/Hu2aTgq@alpha.franken.de>
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在 2023/12/22 12:18, Thomas Bogendoerfer 写道:
> On Fri, Oct 27, 2023 at 11:11:01PM +0100, Jiaxun Yang wrote:
>> Now the exception vector for CPS systems are allocated on-fly
>> with memblock as well.
>>
>> It will try to allocate from KSEG1 first, and then try to allocate
>> in low 4G if possible.
>>
>> The main reset vector is now generated by uasm, to avoid tons
>> of patches to the code. Other vectors are copied to the location
>> later.
> this patch does way to many things in one go. What is needed to
> make a kernel working with an ebase anyware in XPHYS ?

As we have some silly restrictions on the placement of CPS reset_base, it's
impossible to put CPS's cluster reset base "anywhere".

You'll have to make entry code in cps-vec.S relocatable to allow it to 
be moved
by kernel at run time. Either patching the code or generate by uasm.

Thanks
- Jiaxun
>
> Thomas.
>