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Message-ID: <936a4dd1-b595-49b4-ab19-f587a9adb000@flygoat.com>
Date: Fri, 22 Dec 2023 12:47:03 +0000
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Subject: Re: [PATCH v2 07/10] MIPS: traps: Handle CPU with non standard vint
 offset
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To: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Cc: linux-mips@vger.kernel.org, linux-kernel@vger.kernel.org,
 gregory.clement@bootlin.com, vladimir.kondratiev@intel.com
References: <20231027221106.405666-1-jiaxun.yang@flygoat.com>
 <20231027221106.405666-8-jiaxun.yang@flygoat.com>
 <ZYV+zdm4fjYgATVW@alpha.franken.de>
From: Jiaxun Yang <jiaxun.yang@flygoat.com>
In-Reply-To: <ZYV+zdm4fjYgATVW@alpha.franken.de>
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在 2023/12/22 12:19, Thomas Bogendoerfer 写道:
> On Fri, Oct 27, 2023 at 11:11:03PM +0100, Jiaxun Yang wrote:
>> Some BMIPS cpus has none standard start offset for vector interrupts.
>>
>> Handle those CPUs in vector size calculation and handler setup process.
> hmm, I see no connection to what this series is fixing. How does it
> work without this patch ?

In this series reservation of exception vector is moved to here, so it's 
critical
to have correct size.

Thanks
- Jiaxun

>
> Thomas.
>