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Date: Fri, 22 Dec 2023 14:54:19 +0000
From: Conor Dooley <conor@kernel.org>
To: Maxim Kochetkov <fido_max@inbox.ru>
Cc: Christoph Hellwig <hch@lst.de>, Jiaxun Yang <jiaxun.yang@flygoat.com>,
	linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
	robh@kernel.org, mpe@ellerman.id.au, aou@eecs.berkeley.edu,
	palmer@dabbelt.com, paul.walmsley@sifive.com
Subject: Re: [PATCH 1/1] riscv: set ARCH_DMA_DEFAULT_COHERENT if
 RISCV_DMA_NONCOHERENT is not set
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On Fri, Dec 22, 2023 at 05:39:34PM +0300, Maxim Kochetkov wrote:
>=20
>=20
> On 22.12.2023 07:14, Christoph Hellwig wrote:
> > On Thu, Dec 21, 2023 at 10:27:33PM +0000, Jiaxun Yang wrote:
> > >=20
> > >=20
> > > =E5=9C=A8 2023/12/21 20:29, Conor Dooley =E5=86=99=E9=81=93:
> > > > + Christoph
> > > >=20
> > > > I don't think this patch is correct. Regardless of whether we suppo=
rt
> > > > cache management operations, DMA is assumed to be coherent unless
> > > > peripherals etc are specified to otherwise in DT (or however ACPI d=
eals
> > > > with that kind of thing).
> > > >=20
> > > > What problem are you trying to solve here?
> > > >=20
> > > > On Thu, Dec 21, 2023 at 09:51:52PM +0300, Maxim Kochetkov wrote:
> > > > > Not all the RISCV are DMA coherent by default.
> > >=20
> > > Sorry for chime in here.
> > > IMO if your platform is not coherent by default, just insert
> > > "dma-noncoherent"
> > > at devicetree root node.
> >=20
> > Exactly.  ARCH_DMA_DEFAULT_COHERENTis a setting that just says for
> > a given architecture assumes coherent unless otherwise specified,
> > which has historically been the case for mips.  Not setting it means
> > non-coherent unless specified, which has historially been the case
> > for arm.
> >=20
> > RISC-V starte out without support for non-coherent DMA, and high ups
> > in RISCV still told me in 2019 that RISC-V doesn't need cache
> > management instructions because no new hardware would ever not be
> > dma coherent.  Yeah, right..
> >=20
> > Anyay, Linux for RISC-V has historically been coherent only and then
> > coherent default, so this option is wrong, and you need to mark
> > you platform as non-coherent by inserting dma-noncoherent somewhere.
> >=20
> Conor, Christoph, Jiaxun, thanks for quick feedback!
>=20
> The problem is very simple:
> For non mips platforms dma_default_coherent is used at of_dma_is_coherent=
()
> and device_initialize().
> of_dma_is_coherent() affects only DT devices. And we can override it with
> "dma-coherent"/"dma-noncoherent". ACPI devices can specify by
> "attr =3D=3D DEV_DMA_COHERENT". But all other devices (platform_device, u=
sb,

I would have expected that usb devices "inherit" the value from the usb
controller whose bus they are on. Similarly, platform devices are on a
bus that should be marked as non-coherent if that is the case.
Christoph certainly knows better how things operate here however.

> etc..) do not have this feature. These devices will use value from
> device_initialize(). And we have no possibility to change
> dma_default_coherent value by disabling ARCH_DMA_DEFAULT_COHERENT.
> Moreover, changing dma_default_coherent from false to true may cause
> regression for other devices.

How can there be a regression when dma has been coherent by default for
the RISC-V kernel from day 1?

> That is why I suggest possibility to disable
> ARCH_DMA_DEFAULT_COHERENT by RISCV_DMA_NONCOHERENT option.
> It will works like for PPC:
> .....
> config PPC
> 	bool
> 	default y
> 	#
> 	# Please keep this list sorted alphabetically.
> 	#
> 	select ARCH_32BIT_OFF_T if PPC32
> 	select ARCH_DISABLE_KASAN_INLINE	if PPC_RADIX_MMU
> 	select ARCH_DMA_DEFAULT_COHERENT	if !NOT_COHERENT_CACHE
> .....
> Doesn't the option RISCV_DMA_NONCOHERENT say the DMA should be non-cohere=
nt
> by default?

No. That option only controls whether or not support for cache
management operations is built into the kernel. It is expected that this
option can be enabled for multiplatform kernels, like those used by
distributions, that will run on systems that are entirely coherent as
well as those that are not.
It does not work the same was as this PPC option appears to.

Cheers,
Conor.

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