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Message-ID: <e7a5aae4-f3f6-449f-8877-16bfcc880b57@linaro.org>
Date: Tue, 26 Dec 2023 09:24:40 +0100
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Subject: Re: [PATCH] mips: fix r3k_cache_init build regression
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To: Arnd Bergmann <arnd@kernel.org>
Cc: Arnd Bergmann <arnd@arndb.de>, Andrew Morton <akpm@linux-foundation.org>,
 "kernelci . org bot" <bot@kernelci.org>,
 Thomas Bogendoerfer <tsbogend@alpha.franken.de>, Zi Yan <ziy@nvidia.com>,
 Jiaxun Yang <jiaxun.yang@flygoat.com>, linux-mips@vger.kernel.org,
 linux-kernel@vger.kernel.org
References: <20231214205506.310402-1-arnd@kernel.org>
From: =?UTF-8?Q?Philippe_Mathieu-Daud=C3=A9?= <philmd@linaro.org>
In-Reply-To: <20231214205506.310402-1-arnd@kernel.org>
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Hi Arnd,

On 14/12/23 21:54, Arnd Bergmann wrote:
> From: Arnd Bergmann <arnd@arndb.de>
> 
> My earlier patch removed __weak function declarations that used to
> be turned into wild branches by the linker, instead causing
> a link failure when the called functions are unavailable:
> 
> mips-linux-ld: arch/mips/mm/cache.o: in function `cpu_cache_init':
> cache.c:(.text+0x670): undefined reference to `r3k_cache_init'
> 
> The __weak method seems suboptimal, so rather than putting that
> back, make the function calls conditional on the Kconfig symbol
> that controls the compilation.
> 
> Reported-by: kernelci.org bot <bot@kernelci.org>
> Fixes: 66445677f01e ("mips: move cache declarations into header")
> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
> ---
> My broken patch is currently in linux-mm, so the fix should
> be applied on top.
> ---
>   arch/mips/mm/cache.c | 6 +++---
>   1 file changed, 3 insertions(+), 3 deletions(-)
> 
> diff --git a/arch/mips/mm/cache.c b/arch/mips/mm/cache.c
> index e5d19f4a38ba..b7ce73fba998 100644
> --- a/arch/mips/mm/cache.c
> +++ b/arch/mips/mm/cache.c
> @@ -205,14 +205,14 @@ static inline void setup_protection_map(void)
>   
>   void cpu_cache_init(void)
>   {
> -	if (cpu_has_3k_cache) {
> +	if (IS_ENABLED(CONFIG_CPU_R3000) && cpu_has_3k_cache) {
>   		r3k_cache_init();
>   	}
> -	if (cpu_has_4k_cache) {
> +	if (IS_ENABLED(CONFIG_CPU_R4K_CACHE_TLB) && cpu_has_4k_cache) {

Shouldn't we also check for CONFIG_CPU_SB1 enabled?
(See commit 641e97f31887 "Replace SB1 cachecode with standard
R4000 class cache code.")

With that:
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>

>   		r4k_cache_init();
>   	}
>   
> -	if (cpu_has_octeon_cache) {
> +	if (IS_ENABLED(CONFIG_CPU_CAVIUM_OCTEON) && cpu_has_octeon_cache) {
>   		octeon_cache_init();
>   	}
>