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Message-ID: <c2a181b6-089b-44c9-839d-d15b03f1f209@quicinc.com>
Date: Wed, 27 Dec 2023 10:44:58 +0800
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Subject: Re: [PATCH] arm64: dts: qcom: sm8550: Increase supported MSI
 interrupts.
To: Konrad Dybcio <konrad.dybcio@linaro.org>, <andersson@kernel.org>,
        <robh+dt@kernel.org>, <krzysztof.kozlowski+dt@linaro.org>,
        <conor+dt@kernel.org>
CC: <linux-arm-msm@vger.kernel.org>, <devicetree@vger.kernel.org>,
        <linux-kernel@vger.kernel.org>, <quic_cang@quicinc.com>,
        <quic_mrana@quicinc.com>
References: <1703578131-14747-1-git-send-email-quic_qianyu@quicinc.com>
 <3e3c58e0-6501-42c2-874b-1d9a00abb6c7@linaro.org>
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From: Qiang Yu <quic_qianyu@quicinc.com>
In-Reply-To: <3e3c58e0-6501-42c2-874b-1d9a00abb6c7@linaro.org>
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On 12/27/2023 8:26 AM, Konrad Dybcio wrote:
> On 26.12.2023 09:08, Qiang Yu wrote:
>> On sm8550, synopsys MSI controller supports 256 MSI interrupts. Hence,
>> enable all GIC interrupts required by MSI controller for PCIe0 and PCIe1.
>>
>> Signed-off-by: Qiang Yu <quic_qianyu@quicinc.com>
>> ---
> Thanks for digging this up, could you check the same for other platforms
> too? Particularly for the compute ones which heavily depend on PCIe..
In theory, synopsys MSI controller on all Qualcomm platforms supports 256
MSI interrupts. But my current task is to eable them on sm8550. I will
check the same for other platforms and upstream them when I have time.
>
>>   arch/arm64/boot/dts/qcom/sm8550.dtsi | 24 ++++++++++++++++++++----
>>   1 file changed, 20 insertions(+), 4 deletions(-)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi
>> index ee1ba5a..80e31fb 100644
>> --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi
>> @@ -1713,8 +1713,16 @@
>>   			linux,pci-domain = <0>;
>>   			num-lanes = <2>;
>>   
>> -			interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
>> -			interrupt-names = "msi";
>> +			interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
>> +				     <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
>> +				     <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
>> +				     <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
>> +				     <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
>> +				     <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
>> +				     <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
>> +				     <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
>> +			interrupt-names = "msi0", "msi1", "msi2", "msi3",
>> +					  "msi4", "msi5", "msi6", "msi7";
> Please make it one per line, like the interrupts entries.
OK, will modify this part as suggested in next patch. Thanks for your 
review.
>
> Konrad