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Wed, 27 Dec 2023 04:33:23 -0800 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.48 via Frontend Transport; Wed, 27 Dec 2023 04:33:23 -0800 Received: from dc3lp-swdev041.marvell.com (dc3lp-swdev041.marvell.com [10.6.60.191]) by maili.marvell.com (Postfix) with ESMTP id 8D8165B6933; Wed, 27 Dec 2023 04:33:17 -0800 (PST) From: Elad Nachman To: , , , , , , , , , , , , , , , , , , , CC: , Subject: [PATCH 3/4] arm64: dts: ac5: add mmc node and clock Date: Wed, 27 Dec 2023 14:32:56 +0200 Message-ID: <20231227123257.1170590-4-enachman@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20231227123257.1170590-1-enachman@marvell.com> References: <20231227123257.1170590-1-enachman@marvell.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Proofpoint-ORIG-GUID: ewsmlGZgsY4Tm6ZHwAxGaGZEcgmGdzFE X-Proofpoint-GUID: ewsmlGZgsY4Tm6ZHwAxGaGZEcgmGdzFE X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.997,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-12-09_02,2023-12-07_01,2023-05-22_02 From: Elad Nachman Add mmc and mmc clock nodes to ac5 and ac5x device tree files Signed-off-by: Elad Nachman --- arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi | 33 ++++++++++++++++++- 1 file changed, 32 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi b/arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi index b5e042b8e929..decad14d0db8 100644 --- a/arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi +++ b/arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi @@ -77,7 +77,6 @@ soc { #address-cells = <2>; #size-cells = <2>; ranges; - dma-ranges; internal-regs@7f000000 { #address-cells = <1>; @@ -204,6 +203,31 @@ gpio1: gpio@18140 { }; }; + mmc_dma: mmc-dma-peripherals@80500000 { + compatible = "simple-bus"; + #address-cells = <0x2>; + #size-cells = <0x2>; + ranges; + dma-ranges = <0x0 0x0 0x2 0x0 0x0 0x80000000>; + dma-coherent; + + sdhci: mmc@805c0000 { + compatible = "marvell,ac5-sdhci", + "marvell,armada-ap806-sdhci"; + reg = <0x0 0x805c0000 0x0 0x1000>; + interrupts = ; + clocks = <&emmc_clock>, <&cnm_clock>; + clock-names = "core", "axi"; + status = "okay"; + bus-width = <8>; + /*marvell,xenon-phy-slow-mode;*/ + non-removable; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + }; + }; + /* * Dedicated section for devices behind 32bit controllers so we * can configure specific DMA mapping for them @@ -335,5 +359,12 @@ nand_clock: nand-clock { #clock-cells = <0>; clock-frequency = <400000000>; }; + + emmc_clock: emmc_clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <400000000>; + }; + }; }; -- 2.25.1