Received-SPF: pass (google.com: domain of linux-kernel+bounces-12203-linux.lists.archive=gmail.com@vger.kernel.org designates 139.178.88.99 as permitted sender) client-ip=139.178.88.99;
From: Frank Li <Frank.Li@nxp.com>
To: krzysztof.kozlowski@linaro.org
Cc: Frank.Li@nxp.com,
	bhelgaas@google.com,
	conor+dt@kernel.org,
	devicetree@vger.kernel.org,
	festevam@gmail.com,
	helgaas@kernel.org,
	hongxing.zhu@nxp.com,
	imx@lists.linux.dev,
	kernel@pengutronix.de,
	krzysztof.kozlowski+dt@linaro.org,
	kw@linux.com,
	l.stach@pengutronix.de,
	linux-arm-kernel@lists.infradead.org,
	linux-imx@nxp.com,
	linux-kernel@vger.kernel.org,
	linux-pci@vger.kernel.org,
	lpieralisi@kernel.org,
	manivannan.sadhasivam@linaro.org,
	robh@kernel.org,
	s.hauer@pengutronix.de,
	shawnguo@kernel.org
Subject: [PATCH v7 07/16] PCI: imx6: Simplify configure_type() by using mode_off and mode_mask
Date: Wed, 27 Dec 2023 13:27:18 -0500
Message-Id: <20231227182727.1747435-8-Frank.Li@nxp.com>
In-Reply-To: <20231227182727.1747435-1-Frank.Li@nxp.com>
References: <20231227182727.1747435-1-Frank.Li@nxp.com>
Content-Transfer-Encoding: 8bit
Content-Type: text/plain
Precedence: bulk
MIME-Version: 1.0
X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1
X-MS-Exchange-AntiSpam-MessageData-0:
	=?us-ascii?Q?SOv8KpG3Zr6PuouDNMZRt/HlWbbjJ5P4+ngw2po6VMRZtfCDrSC8rc+Xa0UZ?=
 =?us-ascii?Q?H5mK+Eda/bOFSyk3uKpn4mO7u4L5E2amOhLWZMYnY7J09/vS0exO/bZuRd8U?=
 =?us-ascii?Q?GobzmxdNnCUI5f1Pqwo/KPL3r6eME0UHLEaMmLcUPpr5vfKfuLo02yvBMOtN?=
 =?us-ascii?Q?3Oa/I/W+fUENMGmk1eEygwRUoJ6NHyk0SYwmGr7GalP0iGd8Gdnu89b0vj9c?=
 =?us-ascii?Q?n8l3ZeiUgDx2b7xEgzcuXjFYezvg61JIb14DMY6I1Qh99pz33f3FK6QHySOi?=
 =?us-ascii?Q?PHk31F5bqtOWtO7Qgh+8xx8elgYlY97EN3jBOQol+ajlTRC7nz7cyNI/jSPt?=
 =?us-ascii?Q?/WeRjwrHUWdHjNkPwJnYrqN1aEOOrvXN9HDZOdv4zR1UQ/Mx21fAnvLXvsz3?=
 =?us-ascii?Q?kf/no1tG4bl1rampvaa4a93L/yMfZ1hJBvuuRbGKIk+S7zXlgJaiknssIcFf?=
 =?us-ascii?Q?H0F1coij+XdhugpSodZNWhxIY0VYIMF1zZEnYLumj0xSggsjThY2EOlliT7Y?=
 =?us-ascii?Q?FjOO95CsyKZ710b5tQCFuQCQPK7p8/gVnLWS7ATNHFpySC9rA0XknORBdZO7?=
 =?us-ascii?Q?CLYEk7NhMpZpsdt8CPLgPFC/XyGV7CXzSLddXNhnW02p5lJGiHeLKvqOB9QB?=
 =?us-ascii?Q?3CIcpZxukSHXdehJs3Q6yfHVwvGh5te4BM/8pi/EYPr1ryPJVUX1HLsaJz2t?=
 =?us-ascii?Q?aphWXgTMdVoBkpqvXO9KlSgmVLVp1HFQM5EKFmorxLNchxua+pyZYE95m2VO?=
 =?us-ascii?Q?rLQ066X2YqcU4g+nLqtwqL/Rfr7wMNaqRYA5PUQl896MbKrgJuKSoBQMtM9T?=
 =?us-ascii?Q?OBhL+G4E/1DrtNIos17I3p5wDa/AFClE+neJnOkftetUufX+02niPh9c23ea?=
 =?us-ascii?Q?PcflxgmfQaVG1fqH4bFad7vhmB7fqDN3qMOTcZ5ZF8s1l7kjfFTHrOy2zMlN?=
 =?us-ascii?Q?2dCHSrjGNVicbj8opSuYT8P5PUayctQ4t9ie0Nlh/K2VpDMN07EGmpb7eArj?=
 =?us-ascii?Q?T/ItbdGIeU/52G8lG15F+PGIvnZAjBHx41Pegk3bsWY812GdWnmOhXm4r6Pq?=
 =?us-ascii?Q?7ENul/4kUXIgvrnFeQHvTyM+J5I216fAxyv/vLTDOjz0/Aw/ekqQtWsADFEX?=
 =?us-ascii?Q?83VX8+jka9JhdQhTeWX31ocGnifnaoLQUJ1mi90HBVNWCCNI4LgQlxdHl7Ge?=
 =?us-ascii?Q?EmJEF4ebmwcz4syt1PGBX71xH7EUhrv+BiBM9YIUH2EVriMbvLy5fKvrgnSS?=
 =?us-ascii?Q?zMWv/OfmiB3HLcDAqV+7JHz1D/ensjjC5AjBRPArYdTd4yOz6HR7xxop9w9/?=
 =?us-ascii?Q?d6/ZBjgK8SZG+XFasI/5tnEyOTpyTKs6qZY+reuxuQrNzDmFY/f8q2RddcSc?=
 =?us-ascii?Q?68b6uHVIi3CmMmwCb1iheOji8I6Jqr7R4XwIK+lq3/QpmsOqXIOIYd2a88XB?=
 =?us-ascii?Q?8o81fX2hFTbeAuB64iz6aSfKOPB9Bernl2/bQ50FZ7UbXjbO/pjsg1jONRzn?=
 =?us-ascii?Q?Q1y+t1VCblQqgkZ9PQIrBdM5iKj+8worboRz3yiD7nrMN+vYRtKUMLw9Kdr4?=
 =?us-ascii?Q?3Sg9CoAgHzU+++mvpBg=3D?=
X-OriginatorOrg: nxp.com
X-MS-Exchange-CrossTenant-Network-Message-Id: 1a9706ab-457c-4b87-a1b5-08dc07099de4
X-MS-Exchange-CrossTenant-AuthSource: AM6PR04MB4838.eurprd04.prod.outlook.com
X-MS-Exchange-CrossTenant-AuthAs: Internal
X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 Dec 2023 18:28:26.6499
 (UTC)
X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted
X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635
X-MS-Exchange-CrossTenant-MailboxType: HOSTED
X-MS-Exchange-CrossTenant-UserPrincipalName: 9XeHYQJFX4iGO8o8+FI9EFFPSI60f1TDUhGzWqvhrhagZvOjRkWUyBk8l1oOHS26xWuS95+uNKzkHMor6gNc9A==
X-MS-Exchange-Transport-CrossTenantHeadersStamped: DU2PR04MB9050

Add drvdata::mode_off and drvdata::mode_mask to simple
imx6_pcie_configure_type() logic.

Signed-off-by: Frank Li <Frank.Li@nxp.com>
---

Notes:
    Change from v2 to v3
    - none
    Change from v1 to v2
    - use ffs() to fixe build error.

 drivers/pci/controller/dwc/pci-imx6.c | 60 ++++++++++++++++++---------
 1 file changed, 40 insertions(+), 20 deletions(-)

diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c
index 588bfb616260e..717e8fa030deb 100644
--- a/drivers/pci/controller/dwc/pci-imx6.c
+++ b/drivers/pci/controller/dwc/pci-imx6.c
@@ -68,6 +68,7 @@ enum imx6_pcie_variants {
 
 #define IMX6_PCIE_MAX_CLKS       6
 
+#define IMX6_PCIE_MAX_INSTANCES			2
 struct imx6_pcie_drvdata {
 	enum imx6_pcie_variants variant;
 	enum dw_pcie_device_mode mode;
@@ -77,6 +78,8 @@ struct imx6_pcie_drvdata {
 	const char *clk_names[IMX6_PCIE_MAX_CLKS];
 	const u32 ltssm_off;
 	const u32 ltssm_mask;
+	const u32 mode_off[IMX6_PCIE_MAX_INSTANCES];
+	const u32 mode_mask[IMX6_PCIE_MAX_INSTANCES];
 };
 
 struct imx6_pcie {
@@ -174,32 +177,25 @@ static unsigned int imx6_pcie_grp_offset(const struct imx6_pcie *imx6_pcie)
 
 static void imx6_pcie_configure_type(struct imx6_pcie *imx6_pcie)
 {
-	unsigned int mask, val, mode;
+	const struct imx6_pcie_drvdata *drvdata = imx6_pcie->drvdata;
+	unsigned int mask, val, mode, id;
 
-	if (imx6_pcie->drvdata->mode == DW_PCIE_EP_TYPE)
+	if (drvdata->mode == DW_PCIE_EP_TYPE)
 		mode = PCI_EXP_TYPE_ENDPOINT;
 	else
 		mode = PCI_EXP_TYPE_ROOT_PORT;
 
-	switch (imx6_pcie->drvdata->variant) {
-	case IMX8MQ:
-	case IMX8MQ_EP:
-		if (imx6_pcie->controller_id == 1) {
-			mask = IMX8MQ_GPR12_PCIE2_CTRL_DEVICE_TYPE;
-			val  = FIELD_PREP(IMX8MQ_GPR12_PCIE2_CTRL_DEVICE_TYPE,
-					  mode);
-		} else {
-			mask = IMX6Q_GPR12_DEVICE_TYPE;
-			val  = FIELD_PREP(IMX6Q_GPR12_DEVICE_TYPE, mode);
-		}
-		break;
-	default:
-		mask = IMX6Q_GPR12_DEVICE_TYPE;
-		val  = FIELD_PREP(IMX6Q_GPR12_DEVICE_TYPE, mode);
-		break;
-	}
+	id = imx6_pcie->controller_id;
+
+	/* If mode_mask[id] is zero, means each controller have its individual gpr */
+	if (!drvdata->mode_mask[id])
+		id = 0;
+
+	mask = drvdata->mode_mask[id];
+	/* FIELD_PREP mask have been constant */
+	val = mode << (ffs(mask) - 1);
 
-	regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, mask, val);
+	regmap_update_bits(imx6_pcie->iomuxc_gpr, drvdata->mode_off[id], mask, val);
 }
 
 static int pcie_phy_poll_ack(struct imx6_pcie *imx6_pcie, bool exp_val)
@@ -1376,6 +1372,8 @@ static const struct imx6_pcie_drvdata drvdata[] = {
 		.clk_names = {"pcie_bus", "pcie", "pcie_phy"},
 		.ltssm_off = IOMUXC_GPR12,
 		.ltssm_mask = IMX6Q_GPR12_PCIE_CTL_2,
+		.mode_off[0] = IOMUXC_GPR12,
+		.mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE,
 	},
 	[IMX6SX] = {
 		.variant = IMX6SX,
@@ -1386,6 +1384,8 @@ static const struct imx6_pcie_drvdata drvdata[] = {
 		.clk_names = {"pcie_bus", "pcie", "pcie_phy", "pcie_inbound_axi"},
 		.ltssm_off = IOMUXC_GPR12,
 		.ltssm_mask = IMX6Q_GPR12_PCIE_CTL_2,
+		.mode_off[0] = IOMUXC_GPR12,
+		.mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE,
 	},
 	[IMX6QP] = {
 		.variant = IMX6QP,
@@ -1397,6 +1397,8 @@ static const struct imx6_pcie_drvdata drvdata[] = {
 		.clk_names = {"pcie_bus", "pcie", "pcie_phy"},
 		.ltssm_off = IOMUXC_GPR12,
 		.ltssm_mask = IMX6Q_GPR12_PCIE_CTL_2,
+		.mode_off[0] = IOMUXC_GPR12,
+		.mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE,
 	},
 	[IMX7D] = {
 		.variant = IMX7D,
@@ -1405,6 +1407,8 @@ static const struct imx6_pcie_drvdata drvdata[] = {
 			 IMX6_PCIE_FLAG_HAS_PHY_RESET,
 		.gpr = "fsl,imx7d-iomuxc-gpr",
 		.clk_names = {"pcie_bus", "pcie", "pcie_phy"},
+		.mode_off[0] = IOMUXC_GPR12,
+		.mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE,
 	},
 	[IMX8MQ] = {
 		.variant = IMX8MQ,
@@ -1412,6 +1416,10 @@ static const struct imx6_pcie_drvdata drvdata[] = {
 			 IMX6_PCIE_FLAG_HAS_PHY_RESET,
 		.gpr = "fsl,imx8mq-iomuxc-gpr",
 		.clk_names = {"pcie_bus", "pcie", "pcie_phy", "pcie_aux"},
+		.mode_off[0] = IOMUXC_GPR12,
+		.mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE,
+		.mode_off[1] = IOMUXC_GPR12,
+		.mode_mask[1] = IMX8MQ_GPR12_PCIE2_CTRL_DEVICE_TYPE,
 	},
 	[IMX8MM] = {
 		.variant = IMX8MM,
@@ -1420,6 +1428,8 @@ static const struct imx6_pcie_drvdata drvdata[] = {
 			 IMX6_PCIE_FLAG_HAS_APP_RESET,
 		.gpr = "fsl,imx8mm-iomuxc-gpr",
 		.clk_names = {"pcie_bus", "pcie", "pcie_aux"},
+		.mode_off[0] = IOMUXC_GPR12,
+		.mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE,
 	},
 	[IMX8MP] = {
 		.variant = IMX8MP,
@@ -1428,6 +1438,8 @@ static const struct imx6_pcie_drvdata drvdata[] = {
 			 IMX6_PCIE_FLAG_HAS_APP_RESET,
 		.gpr = "fsl,imx8mp-iomuxc-gpr",
 		.clk_names = {"pcie_bus", "pcie", "pcie_aux"},
+		.mode_off[0] = IOMUXC_GPR12,
+		.mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE,
 	},
 	[IMX8MQ_EP] = {
 		.variant = IMX8MQ_EP,
@@ -1436,6 +1448,10 @@ static const struct imx6_pcie_drvdata drvdata[] = {
 		.mode = DW_PCIE_EP_TYPE,
 		.gpr = "fsl,imx8mq-iomuxc-gpr",
 		.clk_names = {"pcie_bus", "pcie", "pcie_phy", "pcie_aux"},
+		.mode_off[0] = IOMUXC_GPR12,
+		.mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE,
+		.mode_off[1] = IOMUXC_GPR12,
+		.mode_mask[1] = IMX8MQ_GPR12_PCIE2_CTRL_DEVICE_TYPE,
 	},
 	[IMX8MM_EP] = {
 		.variant = IMX8MM_EP,
@@ -1443,6 +1459,8 @@ static const struct imx6_pcie_drvdata drvdata[] = {
 		.mode = DW_PCIE_EP_TYPE,
 		.gpr = "fsl,imx8mm-iomuxc-gpr",
 		.clk_names = {"pcie_bus", "pcie", "pcie_aux"},
+		.mode_off[0] = IOMUXC_GPR12,
+		.mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE,
 	},
 	[IMX8MP_EP] = {
 		.variant = IMX8MP_EP,
@@ -1450,6 +1468,8 @@ static const struct imx6_pcie_drvdata drvdata[] = {
 		.mode = DW_PCIE_EP_TYPE,
 		.gpr = "fsl,imx8mp-iomuxc-gpr",
 		.clk_names = {"pcie_bus", "pcie", "pcie_aux"},
+		.mode_off[0] = IOMUXC_GPR12,
+		.mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE,
 	},
 };
 
-- 
2.34.1