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Date: Thu, 28 Dec 2023 13:36:02 +0000
From: Conor Dooley <conor@kernel.org>
To: AnnanLiu <annan.liu.xdu@outlook.com>
Cc: chao.wei@sophgo.com, unicorn_wang@outlook.com, robh+dt@kernel.org,
	krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org,
	paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu,
	devicetree@vger.kernel.org, linux-riscv@lists.infradead.org,
	linux-kernel@vger.kernel.org
Subject: Re: [PATCH] riscv: dts: sophgo: add timer dt node for CV1800
Message-ID: <20231228-distill-heave-ebda9ee53576@spud>
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On Thu, Dec 28, 2023 at 09:06:54PM +0800, AnnanLiu wrote:
> Add the timer device tree node to CV1800 SoC.

> This patch depends on the clk driver and reset driver.
> Clk driver link:
> https://lore.kernel.org/all/IA1PR20MB49539CDAD9A268CBF6CA184BBB9FA@IA1PR2=
0MB4953.namprd20.prod.outlook.com/
> Reset driver link:
> https://lore.kernel.org/all/20231113005503.2423-1-jszhang@kernel.org/

FYI, this stuff should be under the --- line.

If there's nothing else wrong with this commit, I can fix this while
applying.

Cheers,
Conor.

>=20
> Signed-off-by: AnnanLiu <annan.liu.xdu@outlook.com>
> ---
>  arch/riscv/boot/dts/sophgo/cv1800b.dtsi | 72 +++++++++++++++++++++++++
>  1 file changed, 72 insertions(+)
>=20
> diff --git a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi b/arch/riscv/boot/dt=
s/sophgo/cv1800b.dtsi
> index aec6401a467b..34a1647cc51b 100644
> --- a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi
> +++ b/arch/riscv/boot/dts/sophgo/cv1800b.dtsi
> @@ -113,6 +113,78 @@ plic: interrupt-controller@70000000 {
>  			riscv,ndev =3D <101>;
>  		};
> =20
> +		timer0: timer@030a0000 {
> +			compatible =3D "snps,dw-apb-timer";
> +			reg =3D <0x030a0000 0x14>;
> +			interrupts =3D <79 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks =3D <&osc>;
> +			resets =3D <&rst RST_TIMER0>;
> +			status =3D "disabled";
> +		};
> +
> +		timer1: timer@030a0014 {
> +			compatible =3D "snps,dw-apb-timer";
> +			reg =3D <0x030a0014 0x14>;
> +			interrupts =3D <80 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks =3D <&osc>;
> +			resets =3D <&rst RST_TIMER1>;
> +			status =3D "disabled";
> +		};
> +
> +		timer2: timer@030a0028 {
> +			compatible =3D "snps,dw-apb-timer";
> +			reg =3D <0x030a0028 0x14>;
> +			interrupts =3D <81 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks =3D <&osc>;
> +			resets =3D <&rst RST_TIMER2>;
> +			status =3D "disabled";
> +		};
> +
> +		timer3: timer@030a003c {
> +			compatible =3D "snps,dw-apb-timer";
> +			reg =3D <0x030a003c 0x14>;
> +			interrupts =3D <82 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks =3D <&osc>;
> +			resets =3D <&rst RST_TIMER3>;
> +			status =3D "disabled";
> +		};
> +
> +		timer4: timer@030a0050 {
> +			compatible =3D "snps,dw-apb-timer";
> +			reg =3D <0x030a0050 0x14>;
> +			interrupts =3D <83 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks =3D <&osc>;
> +			resets =3D <&rst RST_TIMER4>;
> +			status =3D "disabled";
> +		};
> +
> +		timer5: timer@30a0064 {
> +			compatible =3D "snps,dw-apb-timer";
> +			reg =3D <0x030a0064 0x14>;
> +			interrupts =3D <84 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks =3D <&osc>;
> +			resets =3D <&rst RST_TIMER5>;
> +			status =3D "disabled";
> +		};
> +
> +		timer6: timer@030a0078 {
> +			compatible =3D "snps,dw-apb-timer";
> +			reg =3D <0x030a0078 0x14>;
> +			interrupts =3D <85 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks =3D <&osc>;
> +			resets =3D <&rst RST_TIMER6>;
> +			status =3D "disabled";
> +		};
> +
> +		timer7: timer@030a008c {
> +			compatible =3D "snps,dw-apb-timer";
> +			reg =3D <0x030a008c 0x14>;
> +			interrupts =3D <86 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks =3D <&osc>;
> +			resets =3D <&rst RST_TIMER7>;
> +			status =3D "disabled";
> +		};
> +
>  		clint: timer@74000000 {
>  			compatible =3D "sophgo,cv1800b-clint", "thead,c900-clint";
>  			reg =3D <0x74000000 0x10000>;
> --=20
> 2.34.1
>=20

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