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From: Emil Renner Berthing <emil.renner.berthing@canonical.com>
In-Reply-To: <DM6PR20MB23167E08FCA546D6C1899CB1AB9EA@DM6PR20MB2316.namprd20.prod.outlook.com>
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Date: Thu, 28 Dec 2023 07:47:30 -0600
Message-ID: <CAJM55Z9M=h95d_BJnwV=A6LVK_EtuavMwjPAsyvDtF4wL6vgtg@mail.gmail.com>
Subject: Re: [PATCH] riscv: dts: sophgo: add timer dt node for CV1800
To: AnnanLiu <annan.liu.xdu@outlook.com>, chao.wei@sophgo.com, 
	unicorn_wang@outlook.com, robh+dt@kernel.org, 
	krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, 
	paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu
Cc: devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, 
	linux-kernel@vger.kernel.org
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AnnanLiu wrote:
> Add the timer device tree node to CV1800 SoC.
> This patch depends on the clk driver and reset driver.
> Clk driver link:
> https://lore.kernel.org/all/IA1PR20MB49539CDAD9A268CBF6CA184BBB9FA@IA1PR20MB4953.namprd20.prod.outlook.com/
> Reset driver link:
> https://lore.kernel.org/all/20231113005503.2423-1-jszhang@kernel.org/
>
> Signed-off-by: AnnanLiu <annan.liu.xdu@outlook.com>
> ---
>  arch/riscv/boot/dts/sophgo/cv1800b.dtsi | 72 +++++++++++++++++++++++++
>  1 file changed, 72 insertions(+)
>
> diff --git a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi b/arch/riscv/boot/dts/sophgo/cv1800b.dtsi
> index aec6401a467b..34a1647cc51b 100644
> --- a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi
> +++ b/arch/riscv/boot/dts/sophgo/cv1800b.dtsi
> @@ -113,6 +113,78 @@ plic: interrupt-controller@70000000 {
>  			riscv,ndev = <101>;
>  		};
>
> +		timer0: timer@030a0000 {
> +			compatible = "snps,dw-apb-timer";
> +			reg = <0x030a0000 0x14>;
> +			interrupts = <79 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&osc>;
> +			resets = <&rst RST_TIMER0>;
> +			status = "disabled";
> +		};

Why do all these timers need to be disabled? Usually peripherals like DMA and
internal temperature sensors etc. that don't need any support outside the chip
can just be left on.

> +
> +		timer1: timer@030a0014 {
> +			compatible = "snps,dw-apb-timer";
> +			reg = <0x030a0014 0x14>;
> +			interrupts = <80 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&osc>;
> +			resets = <&rst RST_TIMER1>;
> +			status = "disabled";
> +		};
> +
> +		timer2: timer@030a0028 {
> +			compatible = "snps,dw-apb-timer";
> +			reg = <0x030a0028 0x14>;
> +			interrupts = <81 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&osc>;
> +			resets = <&rst RST_TIMER2>;
> +			status = "disabled";
> +		};
> +
> +		timer3: timer@030a003c {
> +			compatible = "snps,dw-apb-timer";
> +			reg = <0x030a003c 0x14>;
> +			interrupts = <82 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&osc>;
> +			resets = <&rst RST_TIMER3>;
> +			status = "disabled";
> +		};
> +
> +		timer4: timer@030a0050 {
> +			compatible = "snps,dw-apb-timer";
> +			reg = <0x030a0050 0x14>;
> +			interrupts = <83 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&osc>;
> +			resets = <&rst RST_TIMER4>;
> +			status = "disabled";
> +		};
> +
> +		timer5: timer@30a0064 {
> +			compatible = "snps,dw-apb-timer";
> +			reg = <0x030a0064 0x14>;
> +			interrupts = <84 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&osc>;
> +			resets = <&rst RST_TIMER5>;
> +			status = "disabled";
> +		};
> +
> +		timer6: timer@030a0078 {
> +			compatible = "snps,dw-apb-timer";
> +			reg = <0x030a0078 0x14>;
> +			interrupts = <85 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&osc>;
> +			resets = <&rst RST_TIMER6>;
> +			status = "disabled";
> +		};
> +
> +		timer7: timer@030a008c {
> +			compatible = "snps,dw-apb-timer";
> +			reg = <0x030a008c 0x14>;
> +			interrupts = <86 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&osc>;
> +			resets = <&rst RST_TIMER7>;
> +			status = "disabled";
> +		};
> +
>  		clint: timer@74000000 {
>  			compatible = "sophgo,cv1800b-clint", "thead,c900-clint";
>  			reg = <0x74000000 0x10000>;
> --
> 2.34.1
>
>
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