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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 Jan 2024 06:01:43.5901 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 48058cc1-0778-475b-fd8e-08dc0b584bd8 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF000044FB.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB6835 Contains fixes w.r.t usage of LBR Freeze, Erratum 1452 and a bug in the CPU offline path where PMU-related registers are reset. Previous versions can be found at: v1: https://lore.kernel.org/all/cover.1702833179.git.sandipan.das@amd.com/ Changes in v2: - Make the LBR and PMC Freeze feature bit visible in /proc/cpuinfo. As suggested by Stephane, this will be useful to determine if it is feasible to perform kernel FDO on a system. Sandipan Das (3): perf/x86/amd/lbr: Use freeze based on availability perf/x86/amd/lbr: Discard erroneous branch entries perf/x86/amd/core: Avoid register reset when CPU is dead arch/x86/events/amd/core.c | 5 ++--- arch/x86/events/amd/lbr.c | 22 ++++++++++++++-------- arch/x86/include/asm/cpufeatures.h | 2 +- arch/x86/kernel/cpu/scattered.c | 1 + 4 files changed, 18 insertions(+), 12 deletions(-) -- 2.34.1