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From: wenhua lin <wenhua.lin1994@gmail.com>
Date: Tue, 2 Jan 2024 15:29:06 +0800
Message-ID: <CAB9BWhdq92ysEwSGUBP60wZqMPqV59PMhg91rU8r+N983rAHag@mail.gmail.com>
Subject: Re: [PATCH V2 1/2] gpio: pmic-eic-sprd: Two-dimensional arrays
 maintain pmic eic
To: Chunyan Zhang <zhang.lyra@gmail.com>
Cc: Wenhua Lin <Wenhua.Lin@unisoc.com>, Linus Walleij <linus.walleij@linaro.org>, 
	Andy Shevchenko <andy@kernel.org>, Bartosz Golaszewski <brgl@bgdev.pl>, Orson Zhai <orsonzhai@gmail.com>, 
	Baolin Wang <baolin.wang@linux.alibaba.com>, linux-gpio@vger.kernel.org, 
	linux-kernel@vger.kernel.org, Xiongpeng Wu <xiongpeng.wu@unisoc.com>
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On Thu, Sep 28, 2023 at 5:01=E2=80=AFPM Chunyan Zhang <zhang.lyra@gmail.com=
> wrote:
>
> On Thu, 21 Sept 2023 at 20:27, Wenhua Lin <Wenhua.Lin@unisoc.com> wrote:
> >
> > A bank PMIC EIC contains 16 EICs, and the operating registers
> > are BIT0-BIT15, such as BIT0 of the register operated by EIC0.
> > Using the one-dimensional array reg[CACHE_NR_REGS] for maintenance
> > will cause the configuration of other EICs to be affected when
> > operating a certain EIC. In order to solve this problem, the register
> > operation bits of each PMIC EIC are maintained through the two-dimensio=
nal
> > array reg[SPRD_PMIC_EIC_NR][CACHE_NR_REGS] to avoid mutual interference=
.
> >
> > Signed-off-by: Wenhua Lin <Wenhua.Lin@unisoc.com>
> > ---
> >  drivers/gpio/gpio-pmic-eic-sprd.c | 21 +++++++++++----------
> >  1 file changed, 11 insertions(+), 10 deletions(-)
> >
> > diff --git a/drivers/gpio/gpio-pmic-eic-sprd.c b/drivers/gpio/gpio-pmic=
-eic-sprd.c
> > index c3e4d90f6b18..442968bb2490 100644
> > --- a/drivers/gpio/gpio-pmic-eic-sprd.c
> > +++ b/drivers/gpio/gpio-pmic-eic-sprd.c
> > @@ -57,7 +57,7 @@ struct sprd_pmic_eic {
> >         struct gpio_chip chip;
> >         struct regmap *map;
> >         u32 offset;
> > -       u8 reg[CACHE_NR_REGS];
> > +       u8 reg[SPRD_PMIC_EIC_NR][CACHE_NR_REGS];
> >         struct mutex buslock;
> >         int irq;
> >  };
> > @@ -151,8 +151,8 @@ static void sprd_pmic_eic_irq_mask(struct irq_data =
*data)
> >         struct sprd_pmic_eic *pmic_eic =3D gpiochip_get_data(chip);
> >         u32 offset =3D irqd_to_hwirq(data);
> >
> > -       pmic_eic->reg[REG_IE] =3D 0;
> > -       pmic_eic->reg[REG_TRIG] =3D 0;
> > +       pmic_eic->reg[offset][REG_IE] =3D 0;
> > +       pmic_eic->reg[offset][REG_TRIG] =3D 0;
>
> I would suggest just using this one-dimensional array which is enough
> for saving 16-bit values.
>
> To solve the issue mentioned in the commit message, we can set/clear
> the bit according to the value of 'offset', for example:
>
> pmic_eic->reg[REG_IE] &=3D ~BIT(offset);
>
> >
> >         gpiochip_disable_irq(chip, offset);
> >  }
> > @@ -165,8 +165,8 @@ static void sprd_pmic_eic_irq_unmask(struct irq_dat=
a *data)
> >
> >         gpiochip_enable_irq(chip, offset);
> >
> > -       pmic_eic->reg[REG_IE] =3D 1;
> > -       pmic_eic->reg[REG_TRIG] =3D 1;
> > +       pmic_eic->reg[offset][REG_IE] =3D 1;
> > +       pmic_eic->reg[offset][REG_TRIG] =3D 1;
>
> For setting operations:
>
> pmic_eic->reg[REG_IE] |=3D BIT(offset);
>
> >  }
> >
> >  static int sprd_pmic_eic_irq_set_type(struct irq_data *data,
> > @@ -174,13 +174,14 @@ static int sprd_pmic_eic_irq_set_type(struct irq_=
data *data,
> >  {
> >         struct gpio_chip *chip =3D irq_data_get_irq_chip_data(data);
> >         struct sprd_pmic_eic *pmic_eic =3D gpiochip_get_data(chip);
> > +       u32 offset =3D irqd_to_hwirq(data);
> >
> >         switch (flow_type) {
> >         case IRQ_TYPE_LEVEL_HIGH:
> > -               pmic_eic->reg[REG_IEV] =3D 1;
> > +               pmic_eic->reg[offset][REG_IEV] =3D 1;
> >                 break;
> >         case IRQ_TYPE_LEVEL_LOW:
> > -               pmic_eic->reg[REG_IEV] =3D 0;
> > +               pmic_eic->reg[offset][REG_IEV] =3D 0;
> >                 break;
> >         case IRQ_TYPE_EDGE_RISING:
> >         case IRQ_TYPE_EDGE_FALLING:
> > @@ -222,15 +223,15 @@ static void sprd_pmic_eic_bus_sync_unlock(struct =
irq_data *data)
> >                         sprd_pmic_eic_update(chip, offset, SPRD_PMIC_EI=
C_IEV, 1);
> >         } else {
> >                 sprd_pmic_eic_update(chip, offset, SPRD_PMIC_EIC_IEV,
> > -                                    pmic_eic->reg[REG_IEV]);
> > +                                    pmic_eic->reg[offset][REG_IEV]);
>
> When using the array we can deal with it like below since
> sprd_pmic_eic_update() would do a shift for the parameter 'val':
>
> (pmic_eic->reg[REG_IEV] & BIT(offset)) ? 1 : 0;
>

Thank you very much for your review.
I will fix this issue in patch v3.

> >         }
> >
> >         /* Set irq unmask */
> >         sprd_pmic_eic_update(chip, offset, SPRD_PMIC_EIC_IE,
> > -                            pmic_eic->reg[REG_IE]);
> > +                            pmic_eic->reg[offset][REG_IE]);
> >         /* Generate trigger start pulse for debounce EIC */
> >         sprd_pmic_eic_update(chip, offset, SPRD_PMIC_EIC_TRIG,
> > -                            pmic_eic->reg[REG_TRIG]);
> > +                            pmic_eic->reg[offset][REG_TRIG]);
>
> Similar here.
>
> Thanks,
> Chunyan