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Date: Tue, 2 Jan 2024 10:05:51 +0100
From: Johan Hovold <johan@kernel.org>
To: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Cc: Konrad Dybcio <konrad.dybcio@linaro.org>,
	Bjorn Andersson <andersson@kernel.org>,
	Rob Herring <robh+dt@kernel.org>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
	Conor Dooley <conor+dt@kernel.org>,
	Johan Hovold <johan+linaro@kernel.org>,
	Marijn Suijten <marijn.suijten@somainline.org>,
	linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org,
	linux-kernel@vger.kernel.org,
	Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>,
	Konrad Dybcio <konrad.dybcio@somainline.org>
Subject: Re: [PATCH 1/3] arm64: dts: qcom: sc8280xp: Fix PCIe PHY
 power-domains
Message-ID: <ZZPR793E3SoIplLw@hovoldconsulting.com>
References: <20231227-topic-8280_pcie_dts-v1-0-13d12b1698ff@linaro.org>
 <20231227-topic-8280_pcie_dts-v1-1-13d12b1698ff@linaro.org>
 <ZY6sh8nlEUyEfL0u@hovoldconsulting.com>
 <20231229170334.GA9098@thinkpad>
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On Fri, Dec 29, 2023 at 10:33:34PM +0530, Manivannan Sadhasivam wrote:
> On Fri, Dec 29, 2023 at 12:24:55PM +0100, Johan Hovold wrote:
> > On Wed, Dec 27, 2023 at 11:28:26PM +0100, Konrad Dybcio wrote:
> > > The PCIe GDSCs are only related to the RCs. The PCIe PHYs on the other
> > > hand, are powered by VDD_MX and their specific VDDA_PHY/PLL regulators.
> > 
> > No, that does not seem to be entirely correct. I added the power-domains
> > here precisely because they were needed to enable the PHYs.
> > 
> > This is something I stumbled over when trying to figure out how to
> > add support for the second lane pair (i.e. four-lane mode), and I just
> > went back and confirmed that this is still the case.
> > 
> > If you try to enable one of these PHYs without the corresponding GDSC
> > being enabled, you end up with:
> > 
> > [   37.709324] ------------[ cut here ]------------
> > [   37.718196] gcc_pcie_3b_aux_clk status stuck at 'off'
> > [   37.718205] WARNING: CPU: 4 PID: 482 at drivers/clk/qcom/clk-branch.c:86 clk_branch_wait+0x144/0x15c
> > 	
> 
> Technically this patch is correct. PHYs are backed by MX domain only and not
> GDSCs. Only the controllers (PCIe, UFS, USB) are backed by GDSCs. The fact that
> you are seeing issue with PCIe Aux clock suggests me that this clock may not be
> applicable to the PHY but it needs to be enabled for working of the PHY somehow.
> I'll try to find the details on how exactly it is needed.

Sounds good, thanks.

> But if I get the answer like, "This clock is also sourced to PHY directly", then
> we may need to add dual power domain for PHY (both GDSC and MX).

Right.
 
> > Now, you may or may not want to describe the above in the devicetree,
> > but this makes it sound like you're trying to work around an issue with
> > the current Linux implementation.
> > 
> 
> Adding MX domain to PHY in devicetree is definitely not a workaround.

I was referring to the fact that the GDSC domain also appears to be
needed even if that may possible get in the way when trying to implement
suspend.

> It is the
> actual hardware representation. MX is the always on domain, and when CX collapse
> happens during suspend state, it will ensure that all the analog components
> (like PHY) are kept powered on. Otherwise, we will see link down issues.

But if it's an always-on domain as you say, it should not be shut down,
right? Perhaps you still want it described in DT for some other reason.
 
> But, I heard from Qcom that _only_ on this platform, MX is not backing the PCIe
> PHY. I can correlate that with my encounter with PCIe issues after forcing CX
> power collapse.

Ok, but that seems to imply that this patch is definitely *not* correct
(for sc8280xp)?

Johan