Received: by 2002:a05:7412:b995:b0:f9:9502:5bb8 with SMTP id it21csp7127600rdb; Wed, 3 Jan 2024 05:40:04 -0800 (PST) X-Google-Smtp-Source: AGHT+IHAkfHXlxQybX5bX1n3S9ufgPGvl0vTK7xY+GR7lP4KJZm20ZKsQ7QRYi6vRVopjGoEjdus X-Received: by 2002:a05:6358:9106:b0:174:d511:6336 with SMTP id q6-20020a056358910600b00174d5116336mr6110113rwq.55.1704289204068; Wed, 03 Jan 2024 05:40:04 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1704289204; cv=none; d=google.com; s=arc-20160816; b=RxjOXPAJjt71i8QaWI1+p6BjTYZfW/cqFewBXE8v5/h+1axX67cDEGPRuZrh/zhBKq d+B6TuRaqLsHnZ65nF0qDJlKdpYrnoFt671TVkKnCxOXWg9HrflUkGDp2pqwFQn+rkGE H1/LX618S3+xeDmkldS6l97fugeIdNfB/PdGMj4St4ssy+dfTInHEeVZG8MITNCRXWvw SJDhDw2CwKqYIACr7BVkP73DwgEaGHtbt/A9Af2pF45S0ht6gK0r2j+MwvcKRuwHjLsQ F4QmGqcGS21Pw3MC3mnmhbLXY2F43R9tqoHU50SYTy82igCKNN11KR9JJ41xXjRm8k9h riQg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:list-unsubscribe:list-subscribe:list-id:precedence :subject:date:from:dkim-signature; bh=CB6wboZIYsl99NW7ZpENCmNA/cZy6QRen2wbuMMkSvc=; fh=M4SmwWZ/7iHrjhlTFT5OMF7TTciupAxAdgRVURl8aUM=; b=DMxHOmVfhE6IdiO7+BQFMju7N5s2Yg1hlK0oq/GwtWcZ0QvVyDneudnzJnT5lglq8W WSVevX7r7pOHDvAdyqIM3QQ61sAqYuk2Kc9xtRgMhhKMVPpau/G73jFewyUpYUx++UH3 cJ1QR906i3/aNkAwPjoFNElmsu+fc3suumUocbBGNPCjpKaOcZwEQjjJ2jnv50oDLAkp OhAuR0Y35rL7PMUamY1YG6nbrCUlYADn2nKpVPnLWC/FGEOAP9wzNnYWMmqOod95xI7/ RL4PIZGLe/UaZ6tOLFjFQtoYFc8kiq6r1yPag2NnbeH5104o9XKCrHj5MOJMsFcaYqqS X73w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=zb3jTgtH; spf=pass (google.com: domain of linux-kernel+bounces-15598-linux.lists.archive=gmail.com@vger.kernel.org designates 2604:1380:45e3:2400::1 as permitted sender) smtp.mailfrom="linux-kernel+bounces-15598-linux.lists.archive=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from sv.mirrors.kernel.org (sv.mirrors.kernel.org. [2604:1380:45e3:2400::1]) by mx.google.com with ESMTPS id eg10-20020a056a00800a00b006da83a2ceadsi4913156pfb.328.2024.01.03.05.40.03 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Jan 2024 05:40:04 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel+bounces-15598-linux.lists.archive=gmail.com@vger.kernel.org designates 2604:1380:45e3:2400::1 as permitted sender) client-ip=2604:1380:45e3:2400::1; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=zb3jTgtH; spf=pass (google.com: domain of linux-kernel+bounces-15598-linux.lists.archive=gmail.com@vger.kernel.org designates 2604:1380:45e3:2400::1 as permitted sender) smtp.mailfrom="linux-kernel+bounces-15598-linux.lists.archive=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from smtp.subspace.kernel.org (wormhole.subspace.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by sv.mirrors.kernel.org (Postfix) with ESMTPS id 0BF672825D0 for ; Wed, 3 Jan 2024 13:39:51 +0000 (UTC) Received: from localhost.localdomain (localhost.localdomain [127.0.0.1]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 2E24D19BDE; Wed, 3 Jan 2024 13:37:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="zb3jTgtH" X-Original-To: linux-kernel@vger.kernel.org Received: from mail-ed1-f44.google.com (mail-ed1-f44.google.com [209.85.208.44]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B5A811C282 for ; Wed, 3 Jan 2024 13:37:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Received: by mail-ed1-f44.google.com with SMTP id 4fb4d7f45d1cf-554e902064aso8104646a12.1 for ; Wed, 03 Jan 2024 05:37:13 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1704289032; x=1704893832; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=CB6wboZIYsl99NW7ZpENCmNA/cZy6QRen2wbuMMkSvc=; b=zb3jTgtHT7NEq5DsqnBjIzlESY2ELoWRl6I+m014Hodly7YrbsVH3ErEaO74XBBLJv R4Yw2K2WEE2usPyWjbVI/U/CZYdr1zmUeq7oINS18VGVuZ/ec/8IlV0pL/ojbf6a2zhe aQjbnb2LpYA38m+4dYwtiEQ0w1R7SD9b/9Ko33qxxe5nnqe1P4P8nGCcskli5Pi/EaoZ Gt5xR35Gv9p1c9SG/IL+GJm5VI76qQ/AFWYGHVjDG8TXmEbXbBz9dsDhlgyu02/tJ3+1 VN5a9sOiHTfz/SDsX0kfARqk65bRaY7JaaDoMQQky4JlOSw43R+DY0TXrFPXQk58VgWh ZopQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1704289032; x=1704893832; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=CB6wboZIYsl99NW7ZpENCmNA/cZy6QRen2wbuMMkSvc=; b=rclGE6Q+ndBQW8oywMmn6H6o0/pQa0ZRDMIiMprA1mIbQiKlYbIx5w3aQirlXDIacZ bFE2YB8r6kJGcuW/MOMA1/70ex5IrEl40KRA/DluCC2KQpNe8rHK+4ws2cEQwL+V6oZ3 J7bESgsYwNIjqWvZXD/eMKjwhPhR1obYNLIWHgb8/qO9WkKYbKiBv2nrj4VePkb4xu+3 tuS6GO9J61wiKhfNR/PJolP4z7wc6gm/e3Fa3jNb3nOmTZOT1HumArS2oZ6+5oEZ+pou rWPMmAqKSNDkDS5Sfao9SEstIVOH0nwCqli1punDtd9nVtoD6UHSyrOGhVA8hu5RUDXW OWVg== X-Gm-Message-State: AOJu0YyJ8e+HFKo4d79aNVlBI/eTpZVva0PdO+21o29XCYmT3vfG8WoE hfqz3Kxw2m1Ep6WpgaYjXWWLXkGCdIIhvA== X-Received: by 2002:a17:906:59b:b0:9cc:450c:b0d5 with SMTP id 27-20020a170906059b00b009cc450cb0d5mr8142503ejn.4.1704289032149; Wed, 03 Jan 2024 05:37:12 -0800 (PST) Received: from [10.167.154.1] (178235179036.dynamic-4-waw-k-1-3-0.vectranet.pl. [178.235.179.36]) by smtp.gmail.com with ESMTPSA id cl2-20020a170906c4c200b00a275637e699sm6474351ejb.166.2024.01.03.05.37.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Jan 2024 05:37:11 -0800 (PST) From: Konrad Dybcio Date: Wed, 03 Jan 2024 14:36:06 +0100 Subject: [PATCH v5 08/12] clk: qcom: gcc-qcm2290: Unregister critical clocks Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20230717-topic-branch_aon_cleanup-v5-8-99942e6bf1ba@linaro.org> References: <20230717-topic-branch_aon_cleanup-v5-0-99942e6bf1ba@linaro.org> In-Reply-To: <20230717-topic-branch_aon_cleanup-v5-0-99942e6bf1ba@linaro.org> To: Bjorn Andersson , Andy Gross , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1704289018; l=6713; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=StIiRcseer0t+d6QEt9QWDW2dseAKGGF158KsOvOerA=; b=IWucqp1N/H1Oog9EmPW/QTilhhHFeSTCyZm5hk1Tm9H36sdaqvByR8sHM+34bLsGXosteOWLS hLZCVTaWrkECsmnMRdl7X+e85e9dm7gagqC1Zim24GHkNT0qy9yigS+ X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Some clocks need to be always-on, but we don't really do anything with them, other than calling enable() once and telling Linux they're enabled. Unregister them to save a couple of bytes and, perhaps more importantly, allow for runtime suspend of the clock controller device, as CLK_IS_CRITICAL prevents the latter. Signed-off-by: Konrad Dybcio --- drivers/clk/qcom/gcc-qcm2290.c | 106 ++++------------------------------------- 1 file changed, 8 insertions(+), 98 deletions(-) diff --git a/drivers/clk/qcom/gcc-qcm2290.c b/drivers/clk/qcom/gcc-qcm2290.c index 48995e50c6bd..ab281f0d5114 100644 --- a/drivers/clk/qcom/gcc-qcm2290.c +++ b/drivers/clk/qcom/gcc-qcm2290.c @@ -1397,36 +1397,6 @@ static struct clk_branch gcc_cam_throttle_rt_clk = { }, }; -static struct clk_branch gcc_camera_ahb_clk = { - .halt_reg = 0x17008, - .halt_check = BRANCH_HALT_DELAY, - .hwcg_reg = 0x17008, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x17008, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_camera_ahb_clk", - .flags = CLK_IS_CRITICAL, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_camera_xo_clk = { - .halt_reg = 0x17028, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x17028, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_camera_xo_clk", - .flags = CLK_IS_CRITICAL, - .ops = &clk_branch2_ops, - }, - }, -}; - static struct clk_branch gcc_camss_axi_clk = { .halt_reg = 0x58044, .halt_check = BRANCH_HALT, @@ -1825,22 +1795,6 @@ static struct clk_branch gcc_cfg_noc_usb3_prim_axi_clk = { }, }; -static struct clk_branch gcc_disp_ahb_clk = { - .halt_reg = 0x1700c, - .halt_check = BRANCH_HALT, - .hwcg_reg = 0x1700c, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x1700c, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_disp_ahb_clk", - .flags = CLK_IS_CRITICAL, - .ops = &clk_branch2_ops, - }, - }, -}; - static struct clk_regmap_div gcc_disp_gpll0_clk_src = { .reg = 0x17058, .shift = 0, @@ -1899,20 +1853,6 @@ static struct clk_branch gcc_disp_throttle_core_clk = { }, }; -static struct clk_branch gcc_disp_xo_clk = { - .halt_reg = 0x1702c, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x1702c, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_disp_xo_clk", - .flags = CLK_IS_CRITICAL, - .ops = &clk_branch2_ops, - }, - }, -}; - static struct clk_branch gcc_gp1_clk = { .halt_reg = 0x4d000, .halt_check = BRANCH_HALT, @@ -1964,22 +1904,6 @@ static struct clk_branch gcc_gp3_clk = { }, }; -static struct clk_branch gcc_gpu_cfg_ahb_clk = { - .halt_reg = 0x36004, - .halt_check = BRANCH_HALT, - .hwcg_reg = 0x36004, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x36004, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_gpu_cfg_ahb_clk", - .flags = CLK_IS_CRITICAL, - .ops = &clk_branch2_ops, - }, - }, -}; - static struct clk_branch gcc_gpu_gpll0_clk_src = { .halt_check = BRANCH_HALT_DELAY, .clkr = { @@ -2439,22 +2363,6 @@ static struct clk_branch gcc_sdcc2_apps_clk = { }, }; -static struct clk_branch gcc_sys_noc_cpuss_ahb_clk = { - .halt_reg = 0x2b06c, - .halt_check = BRANCH_HALT_VOTED, - .hwcg_reg = 0x2b06c, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x79004, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_sys_noc_cpuss_ahb_clk", - .flags = CLK_IS_CRITICAL, - .ops = &clk_branch2_ops, - }, - }, -}; - static struct clk_branch gcc_sys_noc_usb3_prim_axi_clk = { .halt_reg = 0x1a080, .halt_check = BRANCH_HALT, @@ -2774,8 +2682,6 @@ static struct clk_regmap *gcc_qcm2290_clocks[] = { [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr, [GCC_CAM_THROTTLE_NRT_CLK] = &gcc_cam_throttle_nrt_clk.clkr, [GCC_CAM_THROTTLE_RT_CLK] = &gcc_cam_throttle_rt_clk.clkr, - [GCC_CAMERA_AHB_CLK] = &gcc_camera_ahb_clk.clkr, - [GCC_CAMERA_XO_CLK] = &gcc_camera_xo_clk.clkr, [GCC_CAMSS_AXI_CLK] = &gcc_camss_axi_clk.clkr, [GCC_CAMSS_AXI_CLK_SRC] = &gcc_camss_axi_clk_src.clkr, [GCC_CAMSS_CAMNOC_ATB_CLK] = &gcc_camss_camnoc_atb_clk.clkr, @@ -2816,19 +2722,16 @@ static struct clk_regmap *gcc_qcm2290_clocks[] = { [GCC_CAMSS_TOP_AHB_CLK] = &gcc_camss_top_ahb_clk.clkr, [GCC_CAMSS_TOP_AHB_CLK_SRC] = &gcc_camss_top_ahb_clk_src.clkr, [GCC_CFG_NOC_USB3_PRIM_AXI_CLK] = &gcc_cfg_noc_usb3_prim_axi_clk.clkr, - [GCC_DISP_AHB_CLK] = &gcc_disp_ahb_clk.clkr, [GCC_DISP_GPLL0_CLK_SRC] = &gcc_disp_gpll0_clk_src.clkr, [GCC_DISP_GPLL0_DIV_CLK_SRC] = &gcc_disp_gpll0_div_clk_src.clkr, [GCC_DISP_HF_AXI_CLK] = &gcc_disp_hf_axi_clk.clkr, [GCC_DISP_THROTTLE_CORE_CLK] = &gcc_disp_throttle_core_clk.clkr, - [GCC_DISP_XO_CLK] = &gcc_disp_xo_clk.clkr, [GCC_GP1_CLK] = &gcc_gp1_clk.clkr, [GCC_GP1_CLK_SRC] = &gcc_gp1_clk_src.clkr, [GCC_GP2_CLK] = &gcc_gp2_clk.clkr, [GCC_GP2_CLK_SRC] = &gcc_gp2_clk_src.clkr, [GCC_GP3_CLK] = &gcc_gp3_clk.clkr, [GCC_GP3_CLK_SRC] = &gcc_gp3_clk_src.clkr, - [GCC_GPU_CFG_AHB_CLK] = &gcc_gpu_cfg_ahb_clk.clkr, [GCC_GPU_GPLL0_CLK_SRC] = &gcc_gpu_gpll0_clk_src.clkr, [GCC_GPU_GPLL0_DIV_CLK_SRC] = &gcc_gpu_gpll0_div_clk_src.clkr, [GCC_GPU_IREF_CLK] = &gcc_gpu_iref_clk.clkr, @@ -2869,7 +2772,6 @@ static struct clk_regmap *gcc_qcm2290_clocks[] = { [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr, [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr, [GCC_SDCC2_APPS_CLK_SRC] = &gcc_sdcc2_apps_clk_src.clkr, - [GCC_SYS_NOC_CPUSS_AHB_CLK] = &gcc_sys_noc_cpuss_ahb_clk.clkr, [GCC_SYS_NOC_USB3_PRIM_AXI_CLK] = &gcc_sys_noc_usb3_prim_axi_clk.clkr, [GCC_USB30_PRIM_MASTER_CLK] = &gcc_usb30_prim_master_clk.clkr, [GCC_USB30_PRIM_MASTER_CLK_SRC] = &gcc_usb30_prim_master_clk_src.clkr, @@ -2994,6 +2896,14 @@ static int gcc_qcm2290_probe(struct platform_device *pdev) clk_alpha_pll_configure(&gpll8, regmap, &gpll8_config); clk_alpha_pll_configure(&gpll9, regmap, &gpll9_config); + /* Keep some clocks always-on */ + qcom_branch_set_clk_en(regmap, 0x17008); /* GCC_CAMERA_AHB_CLK */ + qcom_branch_set_clk_en(regmap, 0x17028); /* GCC_CAMERA_XO_CLK */ + qcom_branch_set_clk_en(regmap, 0x1700c); /* GCC_DISP_AHB_CLK */ + qcom_branch_set_clk_en(regmap, 0x1702c); /* GCC_DISP_XO_CLK */ + qcom_branch_set_clk_en(regmap, 0x36004); /* GCC_GPU_CFG_AHB_CLK */ + qcom_branch_set_clk_en(regmap, 0x2b06c); /* GCC_SYS_NOC_CPUSS_AHB_CLK */ + return qcom_cc_really_probe(pdev, &gcc_qcm2290_desc, regmap); } -- 2.43.0