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Date: Wed, 3 Jan 2024 17:30:18 +0000
From: Will Deacon <will@kernel.org>
To: Stephen Rothwell <sfr@canb.auug.org.au>
Cc: Olof Johansson <olof@lixom.net>, Arnd Bergmann <arnd@arndb.de>,
	ARM <linux-arm-kernel@lists.infradead.org>,
	Anshuman Khandual <anshuman.khandual@arm.com>,
	Linus Walleij <linus.walleij@linaro.org>,
	Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
	Linux Next Mailing List <linux-next@vger.kernel.org>
Subject: Re: linux-next: manual merge of the arm-soc tree with the arm-perf
 tree
Message-ID: <20240103173018.GD5954@willie-the-truck>
References: <20240103100324.05f47bb8@canb.auug.org.au>
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On Wed, Jan 03, 2024 at 10:03:24AM +1100, Stephen Rothwell wrote:
> Hi all,
> 
> Today's linux-next merge of the arm-soc tree got a conflict in:
> 
>   arch/arm/kernel/perf_event_v6.c
> 
> between commit:
> 
>   5cd7da19cb97 ("arm: perf: Remove PMU locking")
> 
> from the arm-perf tree and commit:
> 
>   ced296f63635 ("ARM: Delete ARM11MPCore perf leftovers")
> 
> from the arm-soc tree.
> 
> I fixed it up (see below) and can carry the fix as necessary. This
> is now fixed as far as linux-next is concerned, but any non trivial
> conflicts should be mentioned to your upstream maintainer when your tree
> is submitted for merging.  You may also want to consider cooperating
> with the maintainer of the conflicting tree to minimise any particularly
> complex conflicts.
> 
> -- 
> Cheers,
> Stephen Rothwell
> 
> diff --cc arch/arm/kernel/perf_event_v6.c
> index 8fc080c9e4fb,0cbf46233d6b..000000000000
> --- a/arch/arm/kernel/perf_event_v6.c
> +++ b/arch/arm/kernel/perf_event_v6.c
> @@@ -436,35 -386,9 +373,8 @@@ static void armv6pmu_disable_event(stru
>   	val &= ~mask;
>   	val |= evt;
>   	armv6_pmcr_write(val);
>  -	raw_spin_unlock_irqrestore(&events->pmu_lock, flags);
>   }
>   
> - static void armv6mpcore_pmu_disable_event(struct perf_event *event)
> - {
> - 	unsigned long val, mask, evt = 0;
> - 	struct hw_perf_event *hwc = &event->hw;
> - 	int idx = hwc->idx;
> - 
> - 	if (ARMV6_CYCLE_COUNTER == idx) {
> - 		mask	= ARMV6_PMCR_CCOUNT_IEN;
> - 	} else if (ARMV6_COUNTER0 == idx) {
> - 		mask	= ARMV6_PMCR_COUNT0_IEN;
> - 	} else if (ARMV6_COUNTER1 == idx) {
> - 		mask	= ARMV6_PMCR_COUNT1_IEN;
> - 	} else {
> - 		WARN_ONCE(1, "invalid counter number (%d)\n", idx);
> - 		return;
> - 	}
> - 
> - 	/*
> - 	 * Unlike UP ARMv6, we don't have a way of stopping the counters. We
> - 	 * simply disable the interrupt reporting.
> - 	 */
> - 	val = armv6_pmcr_read();
> - 	val &= ~mask;
> - 	val |= evt;
> - 	armv6_pmcr_write(val);
> - }
> - 
>   static int armv6_map_event(struct perf_event *event)
>   {
>   	return armpmu_map_event(event, &armv6_perf_map,

Thanks, this looks fine to me (just remove all the 11MPCore code).

Arnd -- anything you need me to do in the perf tree here other than mention
this in my pull request?

Will