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Message-ID: <54c18d29-3925-4bb6-bf39-ec5cb6dfeedf@intel.com>
Date: Wed, 3 Jan 2024 13:40:38 -0800
User-Agent: Mozilla Thunderbird
Subject: Re: [PATCH v2 2/2] x86/resctrl: Remove hard-coded memory bandwidth
 event configuration
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To: <babu.moger@amd.com>, <corbet@lwn.net>, <fenghua.yu@intel.com>,
	<tglx@linutronix.de>, <mingo@redhat.com>, <bp@alien8.de>,
	<dave.hansen@linux.intel.com>
CC: <x86@kernel.org>, <hpa@zytor.com>, <paulmck@kernel.org>,
	<rdunlap@infradead.org>, <tj@kernel.org>, <peterz@infradead.org>,
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	<kan.liang@linux.intel.com>, <nikunj@amd.com>,
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	<rick.p.edgecombe@intel.com>, <rppt@kernel.org>,
	<maciej.wieczor-retman@intel.com>, <linux-doc@vger.kernel.org>,
	<linux-kernel@vger.kernel.org>, <eranian@google.com>,
	<peternewman@google.com>, <dhagiani@amd.com>
References: <20231201005720.235639-1-babu.moger@amd.com>
 <170240414535.760665.1609957728181418569.stgit@bmoger-ubuntu>
 <d9f3d23d-aba7-4229-bddb-5d6801b22f27@intel.com>
 <978719d8-8492-47f8-afdf-09e7c997b0b3@amd.com>
 <ac9916a9-d83e-46e4-8dee-ecc15775e94c@intel.com>
 <0ac93544-106a-45a9-a3fe-acb107da798b@amd.com>
From: Reinette Chatre <reinette.chatre@intel.com>
In-Reply-To: <0ac93544-106a-45a9-a3fe-acb107da798b@amd.com>
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 =?utf-8?B?MUkrNUR5K0MxMXhGcEJMRzhPb09Da1Y5dzVjZEx5dW91ZEdtSjhCMTB2Ulll?=
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 =?utf-8?B?LzlibFBIRWhHZEZNcVFZaldNeVEyWFN0NFptUGEzcWFaZFFPNjFCRWQyYUlW?=
 =?utf-8?B?djBnQjVDVnVVUThxYjFPdGRIRUZhSFhEemdhRHdBRGVKc0JLaUNFa1pVY1pX?=
 =?utf-8?B?Tk1VMkF0bE44Sm0zTnZ6THo0b1FNTDkyVkpvUGNLVzlSY05XYzlqUVMzTzE3?=
 =?utf-8?B?RmlnSms4amQyOGpkaldsUWNBd2NXb2Q2Z1BLSlVOcVVyRlhwRDFIcXc3RlhL?=
 =?utf-8?B?MEk4Z2tsdVZuY1JCSVhRN1pEUlV4QjVWMzFQSE1zLzNDeE9SWFB1MmFnRzFZ?=
 =?utf-8?B?YWxIZkoyL1dWaGhZUmlBNkcxUjZVQ1NpRXozV29hc0crRWttUTFwb1M1U042?=
 =?utf-8?B?Q25GQTBKRVJ3TW5rSkdmYU0xWkgzMjllaWZvZnJDWTM3dTBkU3JkdEw5Mitu?=
 =?utf-8?B?SmlNK1JIMHU5L0hLVmtmSVF2M2Y5dkZocWFNYWpaM0p2dC9HSWdDUGRvMVo2?=
 =?utf-8?B?TnJKSituSXdZOWVYTmpzSmhmQis2OFFoRmY0MjdzYmNNb25TWkEvQmJGQWhU?=
 =?utf-8?B?VU1pVzVIYVF5OGowYXNMWjVweWJ1bzN2Qk8zNG9wRFVkdm9UeVdKNXBnMjFZ?=
 =?utf-8?B?cDUzQUU4MVFXM1JnMmx6Vm1HY0V4RHF1UTQrTE9VQ0g3ckFVVkxudEJ6OXgx?=
 =?utf-8?B?NjdoaHowbXdrTlJ6elAydldFazh3UVBUenZ2dWppWTVPdHVHQlpieU5ya1hx?=
 =?utf-8?B?a2tBZGdaQmkycU5FY09YZ1BUQ2pwcndDYm5WZENqckgvMjYyblZ2aFRnTjN4?=
 =?utf-8?B?QWhKcXdMNzYxRjRRbEJKQXVJaHhRRkg2S1QybjBkR2dRdnZFWE9sQjlKZmFI?=
 =?utf-8?B?d003eWJqY3RrK2t4dUhUODVqL0NkR0wwU3crY0FJMzRxeS82TGUzQ1NYOUV3?=
 =?utf-8?B?aFNvMVdtbzhVU3NIcUdEVDFoQXJRRlE3Q0VKZ3ZSdlU0TzZzWlpodEJFcE5B?=
 =?utf-8?B?UjZtay83b2tzb3JGdTd0WWFvRm9rVnh6QVZaRWY4VmxoTUM4NWZIbnV5Z2Fu?=
 =?utf-8?B?VXRRRU02Rkg1SE1aUzBPVWxvcjA1VFZ3cHErbWlibmlXZHlwVmZ4N1ovQS82?=
 =?utf-8?B?dXhNb1Z4S1JQb1ZhTEtucmVVQ3dGcFhSdmtLc01JWFFvVk42WUhMbHZIK2lh?=
 =?utf-8?B?b0lmUE93UWoxRWpCUUhheU5qZThaTHBVMEpGa2dLbmMzMFRhZFFKcGRoUFRk?=
 =?utf-8?B?dllzd2xCVGpPTjhHUlo4RzF6alBtcmNoVWU5NkpoRE8xb0s4Y3FQYStGSlll?=
 =?utf-8?B?T1NSTU5tRUlkUDFwM0lLUWRzWXQ3T1hITmM3ZXFUVzRIYU9XRGRuaHJXeFdL?=
 =?utf-8?B?UUV6OGZWd1FzdTBGeGtRVDMvVnY5N0xpb2RhNXgvSlJCOCt5VEFKWk5ZOXRV?=
 =?utf-8?B?NW43TjJUZzdLdVZSZk8xQTgzR3I1WllmWGxvQ0pTeWViWlJiYTEwNStadnJ6?=
 =?utf-8?B?THN2VFR2T3FMSDJRb0wzZDJXaDhVYWRxeElnMEhuQlRIOFIwQndjWWdxS1Rs?=
 =?utf-8?B?ejJuaWNHaC9aWWcwa0ZnVHJ5cStaemRzWTNGeTVUNzBzbzFKdlJMY1ZwN1VR?=
 =?utf-8?B?MXo2WWFXTGFicFhrRVRrdytyM3NBV3Z1QUZ5L00yZ1VmVmMvK2N4eUxXUFhL?=
 =?utf-8?B?cW5pZVlCT3M4TGo2OUI3a2t4bm5XYVpROHdxbG5HWUU4Rm9xbHk4dzhpdkwr?=
 =?utf-8?B?V21XSGt0R2I3RWhUSjNjbEpSRDNOWWRieUlsWWpwK0djNXVvU1V4Y1djMlFl?=
 =?utf-8?B?Q3gwQjdwQWEwWXdhVHVuMHNweStsYkZpTzU1YkE1MDFjTXZ0ZEowWmZmUndH?=
 =?utf-8?B?bENLeEJTNVltUWovbEtyTFZwM2xkOFg2T0pGQjRrRngrNnpzbmhlWDdWeTJE?=
 =?utf-8?B?NkE9PQ==?=
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Hi Babu,

On 1/3/2024 1:03 PM, Moger, Babu wrote:
> On 1/3/24 12:38, Reinette Chatre wrote:
>> On 1/2/2024 12:00 PM, Moger, Babu wrote:
>>> On 12/14/23 19:24, Reinette Chatre wrote:
>>>> On 12/12/2023 10:02 AM, Babu Moger wrote:
>>
>>>>> diff --git a/arch/x86/kernel/cpu/resctrl/monitor.c b/arch/x86/kernel/cpu/resctrl/monitor.c
>>>>> index f136ac046851..30bf919edfda 100644
>>>>> --- a/arch/x86/kernel/cpu/resctrl/monitor.c
>>>>> +++ b/arch/x86/kernel/cpu/resctrl/monitor.c
>>>>> @@ -813,6 +813,12 @@ int __init rdt_get_mon_l3_config(struct rdt_resource *r)
>>>>>  		return ret;
>>>>>  
>>>>>  	if (rdt_cpu_has(X86_FEATURE_BMEC)) {
>>>>> +		u32 eax, ebx, ecx, edx;
>>>>> +
>>>>> +		/* Detect list of bandwidth sources that can be tracked */
>>>>> +		cpuid_count(0x80000020, 3, &eax, &ebx, &ecx, &edx);
>>>>> +		hw_res->event_mask = ecx;
>>>>> +
>>>>
>>>> This has the same issue as I mentioned in V1. Note that this treats
>>>> reserved bits as valid values. I think this is a risky thing to do. For example
>>>> when this code is run on future hardware the currently reserved bits may have
>>>> values with different meaning than what this code uses it for.
>>>
>>> Sure. Will use the mask MAX_EVT_CONFIG_BITS.
>>>               hw_res->mbm_cfg_mask = ecx &  MAX_EVT_CONFIG_BITS;
>>>
>>>>
>>>>>  		if (rdt_cpu_has(X86_FEATURE_CQM_MBM_TOTAL)) {
>>>>>  			mbm_total_event.configurable = true;
>>>>>  			mbm_config_rftype_init("mbm_total_bytes_config");
>>>>> diff --git a/arch/x86/kernel/cpu/resctrl/rdtgroup.c b/arch/x86/kernel/cpu/resctrl/rdtgroup.c
>>>>> index 69a1de92384a..8a1e9fdab974 100644
>>>>> --- a/arch/x86/kernel/cpu/resctrl/rdtgroup.c
>>>>> +++ b/arch/x86/kernel/cpu/resctrl/rdtgroup.c
>>>>> @@ -1537,17 +1537,14 @@ static void mon_event_config_read(void *info)
>>>>>  {
>>>>>  	struct mon_config_info *mon_info = info;
>>>>>  	unsigned int index;
>>>>> -	u64 msrval;
>>>>> +	u32 h;
>>>>>  
>>>>>  	index = mon_event_config_index_get(mon_info->evtid);
>>>>>  	if (index == INVALID_CONFIG_INDEX) {
>>>>>  		pr_warn_once("Invalid event id %d\n", mon_info->evtid);
>>>>>  		return;
>>>>>  	}
>>>>> -	rdmsrl(MSR_IA32_EVT_CFG_BASE + index, msrval);
>>>>> -
>>>>> -	/* Report only the valid event configuration bits */
>>>>> -	mon_info->mon_config = msrval & MAX_EVT_CONFIG_BITS;
>>>>> +	rdmsr(MSR_IA32_EVT_CFG_BASE + index, mon_info->mon_config, h);
>>>>
>>>> I do not think this code needed to be changed. We do not want to treat
>>>> reserved bits as valid values. 
>>>
>>> The logic is still the same. We don't have access to rdt_hw_resource in
>>> this function. So, I just moved the masking to mbm_config_show while printing.
>>
>> Why do you need access to rdt_hw_resource? This comment is not about the bandwidth
>> events supported by the device but instead the bits used to represent these events.
>> This is the same issue as in rdt_get_mon_l3_config. The above change returns
>> reserved bits as valid while the original code ensured that only bits used for
>> field are returned (through the usage of MAX_EVT_CONFIG_BITS).
> 
> We are already saving the valid bits in hw_res->mbm_cfg_mask during the init.
> 
> hw_res->mbm_cfg_mask = ecx &  MAX_EVT_CONFIG_BITS;
> 
> I thought we can use it here directly to mask any unsupported bits. So, I
> re-arranged the code here.

I am not sure where you mean when you say "use it here" since mbm_cfg_mask is not
used in mon_event_config_read(). My comment is related to mon_event_config_read()
that can reasonably be expected to, and thus should, return the current "mon event
config" value and nothing more. 

Reinette