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charset="us-ascii" Content-Transfer-Encoding: quoted-printable Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: DM6PR12MB3993.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 5470966f-9c40-4d86-8900-08dc0ce0ebfa X-MS-Exchange-CrossTenant-originalarrivaltime: 04 Jan 2024 04:52:15.0709 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: NOMBqcR7DAuoOsXxjjtm1AST+fLf61SgEE8YA0pJEE/QeKSa9wS49Qt8fqwC9S82 X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN6PR12MB8541 =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D | Introduction | =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D This document provides a detailed overview of the proposed Kernel feature f= or FPGA Manager subsystem user interface. It describes the problem statement behind the proposal, the problem to be s= olved, a top-level solution design. Table of Contents: ------------------ A. Problem Statement and Background B. Scope and Out of scope of the proposal B.1 Scope B.2 Out of scope C. Proposed Solution D. Proposed User Interface Details =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D | A. Problem Statement and Background = | =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D The existing FPGA manager subsystem didn't have any user space interface (o= ther than the status/state in sysfs) in Kernel.=20 Basically, FPGAs are semiconductor devices that can be reprogrammed for des= ired hardware functionality. FPGAs can be reprogrammed at runtime with different types of logic and IPs = as per user need and hence there is a need to use device tree overlays for = removing/updating/adding the devices at runtime for the IPs/controllers tha= t are present in FPGA.=20 But we don't have any user interface in kernel for updating the device tree= at runtime. Sometime back there was a series sent by Pantelis Antoniou (https://lore.ke= rnel.org/lkml/1414528565-10907-4-git-send-email-pantelis.antoniou@konsulko.= com/). This patch introduced a user interface configfs for Device Tree overlays, a= method of dynamically altering the kernel's live Device Tree. However, th= is patch series was not accepted in mainline due to various concerns. For more details refer to this link: https://elinux.org/Frank%27s_Evolving_= Overlay_Thoughts#issues_and_what_needs_to_be_completed_--_Not_an_exhaustive= _list One of the major valid concerns that were raised with this configfs interfa= ce was security as it opens up the interface to users for modifying the liv= e device tree. So, in order to configure/program the FPGA devices, All the major vendors o= f FPGA are using this configfs series as out-of-tree patch for configuring = the FPGAs and there was never an attempt to introduce a generic interface to configur= e/program the FPGA in upstream and hence upstream kernel ended up in not ha= ving proper support for FPGAs. The proposal below tries to address this gap of FPGA programmability by pro= viding an interface to the user. =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D | B. Proposed Solution | =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D The proposed interface adds a new sysfs interface (of-fpga-region.c) as par= t of the fpga subsystem and it is responsible for supporting the below func= tionalities. --> Provide the user interface for the FPGA subsystem to handle the below F= PGA relevant stuff. - Bridges. - FPGA Configuration. - Driver - Probe/Remove =20 --> The new sysfs interface uses Device Tree overlay (DTO) files to configu= re/ reprogram an FPGA while an operating system is running. - Restrict the overlay's subsystem usage only to FPGA regio= ns in order to mitigate the major security concern with configfs. - Do validation checks on the user provided DTO files. - If the user provided DTO doesn't target a= n FPGA Region which is already part of the running kernel, then return -INV= ALID error. - If the DTO file contains multiple targets= , then return -INVALID error. - It will allow only Child nodes which are = part of targeted FPGA Region. - It avoids Overlay notification calls . So that it will no= t interrupt the other subsystem's(Like; GPIO, I2C.....etc) exists in the ke= rnel. =20 -->This proposed solution will not change the existing sequence When a=20 -->DT overlay that targets an FPGA Region is applied - The FPGA Region will do the following: - 1. Disable appropriate FPGA bridges. - 2. Program the FPGA using the FPGA manager. - 3. Enable the FPGA bridges. - 4. The Device Tree overlay is accepted into the live tree= . - 5. Child devices are populated. - When the overlay is removed, the child nodes will be remo= ved, and the FPGA Region will disable the bridges. =20 . -----= ---------------------------------. .-----------------= ------------------------. =20 | = | | = | | = .------------------| |-------------= --------. | | = | sysfs_load() |<=3D=3D=3D=3D=3D=3D=3D> |Overaly_apply(= )| |=20 .---------------------------------. | = '------------------| |---------------------' = | | | | = | | = | | New Sysfs interface | =3D=3D=3D=3D> | of-fpga-region = .c | | DT Overlay.c = | | load/unload | | = | | = | '--------------------------------' | = .---------------------| |-------------------------.= | | = | sysfs_unload() |<=3D=3D=3D=3D=3D=3D=3D> | Overlay_remove()= | | | = '-------------------- | |--------------= -----------' | | = | | = | '-----= ------------------------------ --' '-----------------= -------------------------' =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D | D. Proposed User Interface Details = | =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D How to use the fpga sysfs interface. To load Image: - echo "DTBO file" > /sys/class/of-fpga_region//load To unload Image: - /sys/class/of-fpga_region//unload To get the image status (Load/Unload): - cat /sys/class/of-fpga_region//status Base Image - Also called the "static image" - An FPGA image that is designed to do full reconfiguration = of the FPGA. - A base image may set up a set of partial reconfiguration r= egions that may later be reprogrammed. .-----------------------. .---------------------= -----------------------. | Host CPU | | FPGA = | | | | = | | -- -| | = ----------- --------- | | | H | | |=3D=3D>| Bri= dge0 |<=3D=3D>| PRR0 | | | | W| | | ----= ------- -------- | | | | | | = | | | B |<=3D=3D=3D=3D=3D> |<=3D=3D | = ----------- -------- | | | R | | |=3D=3D>| Br= idge1 |<=3D=3D>| PRR1| | | | I | | | --= --------- -------- | | | D | | | = | | | G | | | ---= -------- ------- | | | E | | |=3D=3D>| Br= idge2 |<=3D=3D>| PRR2 || | ----| | -= ---------- -------- | | | | = | '-----------------------' '-----------------------= ----------------------' In the above diagram a typical FPGA is setup with a base image that created= three regions. Each region (PRR0 - 2) gets its own split of the busses that is independent= ly gated by a soft logic bridge (Bridge0 - 2) in the FPGA. The contents of each PRR can be reprogrammed independently while the rest o= f the system continues to function. Form the above tropology the sysfs interface looks like as follows. For Base/static region: To load Image: - echo "DTBO file" > /sys/class/of-fpga_region/FPGA/load To unload Image: - /sys/class/of-fpga_region/FPGA/unload To get the image status (Load/Unload): - cat /sys/class/of-fpga_region/FPGA/status For PRR0: To load Image: - echo "DTBO file" > /sys/class/of-fpga_region/PRR0/load To unload Image: - /sys/class/of-fpga_region/PRR0/unload To get the image status (Load/Unload): - cat /sys/class/of-fpga_region/PRR0/status For PRR1: To load Image: - echo "DTBO file" > /sys/class/of-fpga_region/PRR1/load To unload Image: - /sys/class/of-fpga_region/PRR1/unload To get the image status (Load/Unload): - cat /sys/class/of-fpga_region/PRR1/status For PRR1: To load Image: - echo "DTBO file" > /sys/class/of-fpga_region/PRR1/load To unload Image: - /sys/class/of-fpga_region/PRR1/unload To get the image status (Load/Unload): - cat /sys/class/of-fpga_region/PRR1/status