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References: <20240102220134.3229156-1-samuel.holland@sifive.com> <20240102220134.3229156-10-samuel.holland@sifive.com>
In-Reply-To: <20240102220134.3229156-10-samuel.holland@sifive.com>
From: Alexandre Ghiti <alexghiti@rivosinc.com>
Date: Thu, 4 Jan 2024 13:42:55 +0100
Message-ID: <CAHVXubg1=BuA+_BxPb_Q4B1hnN_DvVJ8wyJ_4KmFkU9qNQkWCw@mail.gmail.com>
Subject: Re: [PATCH v4 09/12] riscv: mm: Use a fixed layout for the MM context ID
To: Samuel Holland <samuel.holland@sifive.com>
Cc: Palmer Dabbelt <palmer@dabbelt.com>, linux-riscv@lists.infradead.org, 
	linux-kernel@vger.kernel.org, linux-mm@kvack.org
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On Tue, Jan 2, 2024 at 11:01=E2=80=AFPM Samuel Holland
<samuel.holland@sifive.com> wrote:
>
> Currently, the size of the ASID field in the MM context ID dynamically
> depends on the number of hardware-supported ASID bits. This requires
> reading a global variable to extract either field from the context ID.
> Instead, allocate the maximum possible number of bits to the ASID field,
> so the layout of the context ID is known at compile-time.
>
> Signed-off-by: Samuel Holland <samuel.holland@sifive.com>
> ---
>
> (no changes since v1)
>
>  arch/riscv/include/asm/mmu.h      | 4 ++--
>  arch/riscv/include/asm/tlbflush.h | 2 --
>  arch/riscv/mm/context.c           | 6 ++----
>  3 files changed, 4 insertions(+), 8 deletions(-)
>
> diff --git a/arch/riscv/include/asm/mmu.h b/arch/riscv/include/asm/mmu.h
> index a550fbf770be..dc0273f7905f 100644
> --- a/arch/riscv/include/asm/mmu.h
> +++ b/arch/riscv/include/asm/mmu.h
> @@ -26,8 +26,8 @@ typedef struct {
>  #endif
>  } mm_context_t;
>
> -#define cntx2asid(cntx)                ((cntx) & asid_mask)
> -#define cntx2version(cntx)     ((cntx) & ~asid_mask)
> +#define cntx2asid(cntx)                ((cntx) & SATP_ASID_MASK)
> +#define cntx2version(cntx)     ((cntx) & ~SATP_ASID_MASK)
>
>  void __init create_pgd_mapping(pgd_t *pgdp, uintptr_t va, phys_addr_t pa=
,
>                                phys_addr_t sz, pgprot_t prot);
> diff --git a/arch/riscv/include/asm/tlbflush.h b/arch/riscv/include/asm/t=
lbflush.h
> index d9913590f82e..5bfd37cfd8c3 100644
> --- a/arch/riscv/include/asm/tlbflush.h
> +++ b/arch/riscv/include/asm/tlbflush.h
> @@ -15,8 +15,6 @@
>  #define FLUSH_TLB_NO_ASID       ((unsigned long)-1)
>
>  #ifdef CONFIG_MMU
> -extern unsigned long asid_mask;
> -
>  static inline void local_flush_tlb_all(void)
>  {
>         __asm__ __volatile__ ("sfence.vma" : : : "memory");
> diff --git a/arch/riscv/mm/context.c b/arch/riscv/mm/context.c
> index 43d005f63253..b5170ac1b742 100644
> --- a/arch/riscv/mm/context.c
> +++ b/arch/riscv/mm/context.c
> @@ -22,7 +22,6 @@ DEFINE_STATIC_KEY_FALSE(use_asid_allocator);
>
>  static unsigned long asid_bits;
>  static unsigned long num_asids;
> -unsigned long asid_mask;
>
>  static atomic_long_t current_version;
>
> @@ -128,7 +127,7 @@ static unsigned long __new_context(struct mm_struct *=
mm)
>                 goto set_asid;
>
>         /* We're out of ASIDs, so increment current_version */
> -       ver =3D atomic_long_add_return_relaxed(num_asids, &current_versio=
n);
> +       ver =3D atomic_long_add_return_relaxed(BIT(SATP_ASID_BITS), &curr=
ent_version);
>
>         /* Flush everything  */
>         __flush_context();
> @@ -247,7 +246,6 @@ static int __init asids_init(void)
>         /* Pre-compute ASID details */
>         if (asid_bits) {
>                 num_asids =3D 1 << asid_bits;
> -               asid_mask =3D num_asids - 1;
>         }
>
>         /*
> @@ -255,7 +253,7 @@ static int __init asids_init(void)
>          * at-least twice more than CPUs
>          */
>         if (num_asids > (2 * num_possible_cpus())) {
> -               atomic_long_set(&current_version, num_asids);
> +               atomic_long_set(&current_version, BIT(SATP_ASID_BITS));
>
>                 context_asid_map =3D bitmap_zalloc(num_asids, GFP_KERNEL)=
;
>                 if (!context_asid_map)
> --
> 2.42.0
>

You can add:

Reviewed-by: Alexandre Ghiti <alexghiti@rivosinc.com>

Thanks,

Alex