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References: <20240102220134.3229156-1-samuel.holland@sifive.com> <20240102220134.3229156-13-samuel.holland@sifive.com>
In-Reply-To: <20240102220134.3229156-13-samuel.holland@sifive.com>
From: Alexandre Ghiti <alexghiti@rivosinc.com>
Date: Thu, 4 Jan 2024 14:01:40 +0100
Message-ID: <CAHVXubit8obRHkW9Uw+Ah=1y7cg-_y_8Ho=kzonjLFmeGYZwqQ@mail.gmail.com>
Subject: Re: [PATCH v4 12/12] riscv: mm: Always use an ASID to flush mm contexts
To: Samuel Holland <samuel.holland@sifive.com>
Cc: Palmer Dabbelt <palmer@dabbelt.com>, linux-riscv@lists.infradead.org, 
	linux-kernel@vger.kernel.org, linux-mm@kvack.org
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On Tue, Jan 2, 2024 at 11:01=E2=80=AFPM Samuel Holland
<samuel.holland@sifive.com> wrote:
>
> Even if multiple ASIDs are not supported, using the single-ASID variant
> of the sfence.vma instruction preserves TLB entries for global (kernel)
> pages. So it is always more efficient to use the single-ASID code path.
>
> Signed-off-by: Samuel Holland <samuel.holland@sifive.com>
> ---
>
> Changes in v4:
>  - There is now only one copy of __flush_tlb_range()
>
> Changes in v2:
>  - Update both copies of __flush_tlb_range()
>
>  arch/riscv/include/asm/mmu_context.h | 2 --
>  arch/riscv/mm/context.c              | 3 +--
>  arch/riscv/mm/tlbflush.c             | 3 +--
>  3 files changed, 2 insertions(+), 6 deletions(-)
>
> diff --git a/arch/riscv/include/asm/mmu_context.h b/arch/riscv/include/as=
m/mmu_context.h
> index 7030837adc1a..b0659413a080 100644
> --- a/arch/riscv/include/asm/mmu_context.h
> +++ b/arch/riscv/include/asm/mmu_context.h
> @@ -33,8 +33,6 @@ static inline int init_new_context(struct task_struct *=
tsk,
>         return 0;
>  }
>
> -DECLARE_STATIC_KEY_FALSE(use_asid_allocator);
> -
>  #include <asm-generic/mmu_context.h>
>
>  #endif /* _ASM_RISCV_MMU_CONTEXT_H */
> diff --git a/arch/riscv/mm/context.c b/arch/riscv/mm/context.c
> index 3ca9b653df7d..20057085ab8a 100644
> --- a/arch/riscv/mm/context.c
> +++ b/arch/riscv/mm/context.c
> @@ -18,8 +18,7 @@
>
>  #ifdef CONFIG_MMU
>
> -DEFINE_STATIC_KEY_FALSE(use_asid_allocator);
> -
> +static DEFINE_STATIC_KEY_FALSE(use_asid_allocator);
>  static unsigned long num_asids;
>
>  static atomic_long_t current_version;
> diff --git a/arch/riscv/mm/tlbflush.c b/arch/riscv/mm/tlbflush.c
> index 5ec621545c69..39d80f56d292 100644
> --- a/arch/riscv/mm/tlbflush.c
> +++ b/arch/riscv/mm/tlbflush.c
> @@ -84,8 +84,7 @@ static void __flush_tlb_range(struct mm_struct *mm, uns=
igned long start,
>                 if (cpumask_empty(cmask))
>                         return;
>
> -               if (static_branch_unlikely(&use_asid_allocator))
> -                       asid =3D cntx2asid(atomic_long_read(&mm->context.=
id));
> +               asid =3D cntx2asid(atomic_long_read(&mm->context.id));
>         } else {
>                 cmask =3D cpu_online_mask;
>         }
> --
> 2.42.0
>

You can add:

Reviewed-by: Alexandre Ghiti <alexghiti@rivosinc.com>

Thanks!

Alex