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Message-ID: <641e8800-4735-406b-8555-d4a80201f0b9@linaro.org>
Date: Thu, 4 Jan 2024 14:22:12 +0000
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Subject: Re: [PATCH] clk: qcom: dispcc-sdm845: Adjust internal GDSC wait times
Content-Language: en-US
To: Konrad Dybcio <konrad.dybcio@linaro.org>,
 Bjorn Andersson <andersson@kernel.org>,
 Michael Turquette <mturquette@baylibre.com>, Stephen Boyd
 <sboyd@kernel.org>, Taniya Das <quic_tdas@quicinc.com>
Cc: Marijn Suijten <marijn.suijten@somainline.org>,
 linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org,
 linux-kernel@vger.kernel.org
References: <20240103-topic-845gdsc-v1-1-368efbe1a61d@linaro.org>
From: Caleb Connolly <caleb.connolly@linaro.org>
In-Reply-To: <20240103-topic-845gdsc-v1-1-368efbe1a61d@linaro.org>
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On 03/01/2024 20:20, Konrad Dybcio wrote:
> SDM845 downstream uses non-default values for GDSC internal waits.
> Program them accordingly to avoid surprises.
> 
> Fixes: 81351776c9fb ("clk: qcom: Add display clock controller driver for SDM845")
> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>

This doesn't break anything, but I'm not exactly sure what it fixes :P

Tested-by: Caleb Connolly <caleb.connolly@linaro.org> # OnePlus 6
> ---
>  drivers/clk/qcom/dispcc-sdm845.c | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/drivers/clk/qcom/dispcc-sdm845.c b/drivers/clk/qcom/dispcc-sdm845.c
> index 735adfefc379..e792e0b130d3 100644
> --- a/drivers/clk/qcom/dispcc-sdm845.c
> +++ b/drivers/clk/qcom/dispcc-sdm845.c
> @@ -759,6 +759,8 @@ static struct clk_branch disp_cc_mdss_vsync_clk = {
>  
>  static struct gdsc mdss_gdsc = {
>  	.gdscr = 0x3000,
> +	.en_few_wait_val = 0x6,
> +	.en_rest_wait_val = 0x5,
>  	.pd = {
>  		.name = "mdss_gdsc",
>  	},
> 
> ---
> base-commit: 0fef202ac2f8e6d9ad21aead648278f1226b9053
> change-id: 20240103-topic-845gdsc-bcd9d549f153
> 
> Best regards,

-- 
// Caleb (they/them)